Patents by Inventor JungHwan Hwang

JungHwan Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10748471
    Abstract: A gate driving circuit comprising stages cascade-connected with each other and configured to output gate signals, a stage of the stages including a pull-up circuit configured to output a high voltage of a clock signal as a high voltage of a gate signal in response to a bootstrap voltage of a control node in a period of a frame period, a first discharging circuit configured to discharge a voltage of the control node to a first low voltage in response to a carry signal of at least one stage of the plurality of stages that is subsequent to the stage, and a second discharging circuit configured to discharge a voltage of the control node to a second low voltage being lower than the first low voltage in response to a carry signal of at least one stage of the plurality of stages that is subsequent to the stage.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: August 18, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Junghwan Hwang
  • Patent number: 10733950
    Abstract: A gate driving circuit includes: a plurality of stages to provide gate signals to gate lines of a display panel, a k-th stage, where k is a natural number greater than or equal to 2, from among the plurality of stages being configured: to receive a clock signal, a (k?1)th carry signal from a (k?1)th stage, a (k+1)th carry signal from a (k+1)th stage, a (k+2)th carry signal from a (k+2)th stage, a first voltage, and a second voltage, the clock signal being a pulse signal in which a high voltage and a third voltage appear periodically, and the third voltage having a lower voltage level than those of the first voltage and the second voltage; and to output a k-th gate signal and a k-th carry signal.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: August 4, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Junghwan Hwang, Sehyoung Cho
  • Publication number: 20200126486
    Abstract: A display device includes: a display panel including data lines, gate lines, and pixels, the display panel is operated in an active period or in a blank period; and a driving circuit for driving the display panel, the driving circuit including: a signal controller for outputting clock control signals; a voltage generator for receiving the clock control signals, wherein the voltage generator outputs active clock signals synchronized with the clock control signals during the active period and outputs blank clock signals during the blank period; and an overcurrent detection circuit for receiving the clock control signals and the blank clock signals, the overcurrent detection circuit detects an overcurrent of the blank clock signals, and a phase difference between the clock control signals in the active period is different from a phase difference between the clock control signals in the blank period.
    Type: Application
    Filed: December 19, 2019
    Publication date: April 23, 2020
    Inventors: YANGUK NAM, Dae-sik LEE, Yoomi KIM, Junghwan HWANG
  • Publication number: 20200066224
    Abstract: A display device to display an image during frame intervals, and to display a blank image during a blank interval defined between the frame intervals, includes: a gate driving circuit including a plurality of stages, an ith stage (i is an integer greater than or equal to 2) from among the plurality of stages including a clock terminal to receive a clock signal, wherein the clock signal swings between a first clock voltage and a second clock voltage smaller than the first clock voltage during a normal interval corresponding to each of the frame intervals, and the clock signal is changed to a voltage lower than the second clock voltage during a stabilization interval corresponding to the blank interval.
    Type: Application
    Filed: October 28, 2019
    Publication date: February 27, 2020
    Inventors: Junghwan Hwang, Chanwook Shim, Youngchul Jo
  • Patent number: 10515592
    Abstract: A display device includes: a display panel including data lines, gate lines, and pixels, the display panel is operated in an active period or in a blank period; and a driving circuit for driving the display panel, the driving circuit including: a signal controller for outputting clock control signals; a voltage generator for receiving the clock control signals, wherein the voltage generator outputs active clock signals synchronized with the clock control signals during the active period and outputs blank clock signals during the blank period; and an overcurrent detection circuit for receiving the clock control signals and the blank clock signals, the overcurrent detection circuit detects an overcurrent of the blank clock signals, and a phase difference between the clock control signals in the active period is different from a phase difference between the clock control signals in the blank period.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: December 24, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yanguk Nam, Dae-sik Lee, Yoomi Kim, Junghwan Hwang
  • Patent number: 10488717
    Abstract: A display apparatus includes a first substrate, a first dummy substrate on the first substrate, and a second dummy substrate extending from the first dummy substrate and bent. The second dummy substrate is on different side surfaces of the first substrate in a first direction. The display apparatus also includes a plurality of pixels on the first dummy substrate, a gate driver on the second dummy substrate and connected to the pixels, and a data driver connected to one side of the first dummy substrate in a second direction crossing the first direction and connected to the pixels.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: November 26, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kwihyun Kim, Jongjae Lee, Junghwan Hwang, Jongdo Keum, Yoonsik Park, Hongmin Yoon
  • Publication number: 20190340991
    Abstract: A gate driving circuit includes: a plurality of stages to provide gate signals to gate lines of a display panel, a k-th stage, where k is a natural number greater than or equal to 2, from among the plurality of stages being configured: to receive a clock signal, a (k?1)th carry signal from a (k?1)th stage, a (k+1)th carry signal from a (k+1)th stage, a (k+2)th carry signal from a (k+2)th stage, a first voltage, and a second voltage, the clock signal being a pulse signal in which a high voltage and a third voltage appear periodically, and the third voltage having a lower voltage level than those of the first voltage and the second voltage; and to output a k-th gate signal and a k-th carry signal.
    Type: Application
    Filed: July 22, 2019
    Publication date: November 7, 2019
    Inventors: Junghwan HWANG, Sehyoung CHO
  • Patent number: 10460691
    Abstract: A display device to display an image during frame intervals, and to display a blank image during a blank interval defined between the frame intervals, includes: a gate driving circuit including a plurality of stages, an ith stage (i is an integer greater than or equal to 2) from among the plurality of stages including a clock terminal to receive a clock signal, wherein the clock signal swings between a first clock voltage and a second clock voltage smaller than the first clock voltage during a normal interval corresponding to each of the frame intervals, and the clock signal is changed to a voltage lower than the second clock voltage during a stabilization interval corresponding to the blank interval.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: October 29, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Junghwan Hwang, Chanwook Shim, Youngchul Jo
  • Patent number: 10360863
    Abstract: A gate driving circuit includes: a plurality of stages to provide gate signals to gate lines of a display panel, a k-th stage, where k is a natural number greater than or equal to 2, from among the plurality of stages being configured: to receive a clock signal, a (k?1)th carry signal from a (k?1)th stage, a (k+1)th carry signal from a (k+1)th stage, a (k+2)th carry signal from a (k+2)th stage, a first voltage, and a second voltage, the clock signal being a pulse signal in which a high voltage and a third voltage appear periodically, and the third voltage having a lower voltage level than those of the first voltage and the second voltage; and to output a k-th gate signal and a k-th carry signal.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: July 23, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Junghwan Hwang, Sehyoung Cho
  • Publication number: 20190214172
    Abstract: A dust core includes soft magnetic particles, a first coating layer, a second coating layer, and a third coating layer. The first coating layer is made of aluminum oxide with which at least a part of surfaces of the soft magnetic particles are coated. The second coating layer is made of aluminum nitride with which at least a part of a surface of the first coating layer is coated. The third coating layer is made of low-melting-point glass with which at least a part of a surface of the second coating layer is coated. The low-melting-point glass has a softening point lower than an annealing temperature of the soft magnetic particles.
    Type: Application
    Filed: March 18, 2019
    Publication date: July 11, 2019
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masashi OHTSUBO, Masaaki TANI, Takeshi HATTORI, Junghwan HWANG, Masashi HARA, Shin TAJIMA, Shinjiro SAIGUSA, Kohei ISHII, Daisuke OKAMOTO, Toshimitsu TAKAHASHI
  • Publication number: 20190206303
    Abstract: A gate driving circuit comprising stages cascade-connected with each other and configured to output gate signals, a stage of the stages including a pull-up circuit configured to output a high voltage of a clock signal as a high voltage of a gate signal in response to a bootstrap voltage of a control node in a period of a frame period, a first discharging circuit configured to discharge a voltage of the control node to a first low voltage in response to a carry signal of at least one stage of the plurality of stages that is subsequent to the stage, and a second discharging circuit configured to discharge a voltage of the control node to a second low voltage being lower than the first low voltage in response to a carry signal of at least one stage of the plurality of stages that is subsequent to the stage.
    Type: Application
    Filed: December 27, 2018
    Publication date: July 4, 2019
    Inventor: Junghwan HWANG
  • Publication number: 20190122611
    Abstract: A display device includes: a display panel including data lines, gate lines, and pixels, the display panel is operated in an active period or in a blank period; and a driving circuit for driving the display panel, the driving circuit including: a signal controller for outputting clock control signals; a voltage generator for receiving the clock control signals, wherein the voltage generator outputs active clock signals synchronized with the clock control signals during the active period and outputs blank clock signals during the blank period; and an overcurrent detection circuit for receiving the clock control signals and the blank clock signals, the overcurrent detection circuit detects an overcurrent of the blank clock signals, and a phase difference between the clock control signals in the active period is different from a phase difference between the clock control signals in the blank period.
    Type: Application
    Filed: July 24, 2018
    Publication date: April 25, 2019
    Inventors: YANGUK NAM, Dae-sik Lee, Yoomi Kim, Junghwan Hwang
  • Patent number: 9941039
    Abstract: A soft magnetic member is formed such that, when a differential relative permeability in an applied magnetic field of 100 A/m is represented by a first differential relative permeability ??L, and when a differential relative permeability in an applied magnetic field of 40 kA/m is represented by a second differential relative permeability ??H, a ratio of the first differential relative permeability ??L to the second differential relative permeability ??H satisfies a relationship of ??L/??H?10, and a magnetic flux density in an applied magnetic field of 60 kA/m is 1.15 T or higher.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: April 10, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Daisuke Okamoto, Kiyotaka Onodera, Shinjiro Saigusa, Kohei Ishii, Masashi Ohtsubo, Junghwan Hwang, Masaaki Tani, Takeshi Hattori
  • Publication number: 20170343868
    Abstract: A display apparatus includes a first substrate, a first dummy substrate on the first substrate, and a second dummy substrate extending from the first dummy substrate and bent. The second dummy substrate is on different side surfaces of the first substrate in a first direction. The display apparatus also includes a plurality of pixels on the first dummy substrate, a gate driver on the second dummy substrate and connected to the pixels, and a data driver connected to one side of the first dummy substrate in a second direction crossing the first direction and connected to the pixels.
    Type: Application
    Filed: December 16, 2016
    Publication date: November 30, 2017
    Inventors: Kwihyun KIM, Jongjae LEE, Junghwan HWANG, Jongdo KEUM, Yoonsik PARK, Hongmin YOON
  • Publication number: 20170110076
    Abstract: A gate driving circuit includes: a plurality of stages to provide gate signals to gate lines of a display panel, a k-th stage, where k is a natural number greater than or equal to 2, from among the plurality of stages being configured: to receive a clock signal, a (k?1)th carry signal from a (k?1)th stage, a (k+1)th carry signal from a (k+1)th stage, a (k+2)th carry signal from a (k+2)th stage, a first voltage, and a second voltage, the clock signal being a pulse signal in which a high voltage and a third voltage appear periodically, and the third voltage having a lower voltage level than those of the first voltage and the second voltage; and to output a k-th gate signal and a k-th carry signal.
    Type: Application
    Filed: August 3, 2016
    Publication date: April 20, 2017
    Inventors: Junghwan Hwang, Sehyoung Cho
  • Patent number: 9618963
    Abstract: Disclosed is a power management apparatus and a multi-source energy harvesting system using the apparatus, which manage power supplied by individual harvesting sources without wasting the power, thus efficiently distributing the power to a battery. The power management apparatus includes a plurality of comparison units configured to compare voltages of storage devices respectively connected to output terminals of a plurality of harvesting power sources with a preset threshold voltage. A control unit is configured to control an operation of the power management apparatus. A plurality of switching units are installed between the storage devices and a battery and are configured to be turned on/off in response to switching control signals output from the control unit and to form power transmission paths between corresponding storage devices and the battery. The control unit generates and provides the switching control signals based on output signals of the comparison units.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: April 11, 2017
    Assignee: ELECRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Taewook Kang, Sungeun Kim, Kyunghwan Park, Sungweon Kang, Taeyoung Kang, Kyungsoo Kim, Jungbum Kim, Hyungil Park, Ingi Lim, Byounggun Choi, Changhee Hyoung, Junghwan Hwang
  • Publication number: 20170084245
    Abstract: A display device to display an image during frame intervals, and to display a blank image during a blank interval defined between the frame intervals, includes: a gate driving circuit including a plurality of stages, an ith stage (i is an integer greater than or equal to 2) from among the plurality of stages including a clock terminal to receive a clock signal, wherein the clock signal swings between a first clock voltage and a second clock voltage smaller than the first clock voltage during a normal interval corresponding to each of the frame intervals, and the clock signal is changed to a voltage lower than the second clock voltage during a stabilization interval corresponding to the blank interval.
    Type: Application
    Filed: May 23, 2016
    Publication date: March 23, 2017
    Inventors: Junghwan Hwang, Chanwook Shim, Youngchul Jo
  • Publication number: 20160071636
    Abstract: A dust core includes soft magnetic particles, a first coating layer, a second coating layer, and a third coating layer. The first coating layer is made of aluminum oxide with which at least a part of surfaces of the soft magnetic particles are coated. The second coating layer is made of aluminum nitride with which at least a part of a surface of the first coating layer is coated. The third coating layer is made of low-melting-point glass with which at least a part of a surface of the second coating layer is coated. The low-melting-point glass has a softening point lower than an annealing temperature of the soft magnetic particles.
    Type: Application
    Filed: September 8, 2015
    Publication date: March 10, 2016
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masashi OHTSUBO, Masaaki Tani, Takeshi Hattori, Junghwan Hwang, Masashi Hara, Shin Tajima, Shinjiro Saigusa, Kohei Ishii, Daisuke Okamoto, Toshimitsu Takahashi
  • Publication number: 20150364235
    Abstract: A soft magnetic member is formed such that, when a differential relative permeability in an applied magnetic field of 100 A/m is represented by a first differential relative permeability ??L, and when a differential relative permeability in an applied magnetic field of 40 kA/m is represented by a second differential relative permeability ??H, a ratio of the first differential relative permeability ??L to the second differential relative permeability ??H satisfies a relationship of ??L/??H?10, and a magnetic flux density in an applied magnetic field of 60 kA/m is 1.15 T or higher.
    Type: Application
    Filed: June 12, 2015
    Publication date: December 17, 2015
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Daisuke OKAMOTO, Kiyotaka ONODERA, Shinjiro SAIGUSA, Kohei ISHII, Masashi OHTSUBO, Junghwan HWANG, Masaaki TANI, Takeshi HATTORI
  • Patent number: 9159489
    Abstract: The invention includes: powder preparation step of obtaining magnetic core powders by mixing, of magnetic powders with thermosetting resin powders in hot state; powder filling step of filling the obtained magnetic core powders into a die; a compaction step of compacting magnetic core powders; and compact heating step of heating, compacts to the elevated temperature state at which the thermosetting resin hardens after compaction.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: October 13, 2015
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Junghwan Hwang, Takeshi Hattori, Masaki Hirano, Masaki Sugiyama, Yusuke Oishi, Daisuke Okamoto, Hidenari Yamamoto