Abstract: The present disclosure provides a display device. The display device includes a display panel including each of gate lines extending in a first direction, each of sub-gate lines which extends in a second direction crossing the first direction and is electrically connected to the gate line, each of first data lines, each of second data lines, each of first pixels, and each of second pixels, and a driving circuit for providing a gate signal and data signals, wherein a second capacitance between a second drain electrode and a second gate electrode of the second pixel is greater than a first capacitance between a first drain electrode and a first gate electrode of the first pixel.

Abstract: A gate driver includes a plurality of active stages and a plurality of dummy stages. The active stage is configured to output a plurality of gate signals to a display region. The dummy stage is c connected to respective active stages and configured to output a plurality of dummy carry signals to the respective active stages. The active stage is configured to output the plurality of gate signals and a plurality of active carry signals. The plurality of dummy stages are configured to output the plurality of dummy carry signals, respectively, and not to output any gate signal.

Abstract: The present disclosure provides a display device. The display device includes a display panel including each of gate lines extending in a first direction, each of sub-gate lines which extends in a second direction crossing the first direction and is electrically connected to the gate line, each of first data lines, each of second data lines, each of first pixels, and each of second pixels, and a driving circuit for providing a gate signal and data signals, wherein a second capacitance between a second drain electrode and a second gate electrode of the second pixel is greater than a first capacitance between a first drain electrode and a first gate electrode of the first pixel.

Abstract: A display device includes: a display panel including data lines, gate lines, and pixels, the display panel is operated in an active period or in a blank period; and a driving circuit for driving the display panel, the driving circuit including: a signal controller for outputting clock control signals; a voltage generator for receiving the clock control signals, wherein the voltage generator outputs active clock signals synchronized with the clock control signals during the active period and outputs blank clock signals during the blank period; and an overcurrent detection circuit for receiving the clock control signals and the blank clock signals, the overcurrent detection circuit detects an overcurrent of the blank clock signals, and a phase difference between the clock control signals in the active period is different from a phase difference between the clock control signals in the blank period.

Abstract: A display device to display an image during frame intervals, and to display a blank image during a blank interval defined between the frame intervals, includes: a gate driving circuit including a plurality of stages, an ith stage (i is an integer greater than or equal to 2) from among the plurality of stages including a clock terminal to receive a clock signal, wherein the clock signal swings between a first clock voltage and a second clock voltage smaller than the first clock voltage during a normal interval corresponding to each of the frame intervals, and the clock signal is changed to a voltage lower than the second clock voltage during a stabilization interval corresponding to the blank interval.

Abstract: A gate driving circuit comprising stages cascade-connected with each other and configured to output gate signals, a stage of the stages including a pull-up circuit configured to output a high voltage of a clock signal as a high voltage of a gate signal in response to a bootstrap voltage of a control node in a period of a frame period, a first discharging circuit configured to discharge a voltage of the control node to a first low voltage in response to a carry signal of at least one stage of the plurality of stages that is subsequent to the stage, and a second discharging circuit configured to discharge a voltage of the control node to a second low voltage being lower than the first low voltage in response to a carry signal of at least one stage of the plurality of stages that is subsequent to the stage.

Abstract: A gate driving circuit includes: a plurality of stages to provide gate signals to gate lines of a display panel, a k-th stage, where k is a natural number greater than or equal to 2, from among the plurality of stages being configured: to receive a clock signal, a (k?1)th carry signal from a (k?1)th stage, a (k+1)th carry signal from a (k+1)th stage, a (k+2)th carry signal from a (k+2)th stage, a first voltage, and a second voltage, the clock signal being a pulse signal in which a high voltage and a third voltage appear periodically, and the third voltage having a lower voltage level than those of the first voltage and the second voltage; and to output a k-th gate signal and a k-th carry signal.

Abstract: A display device includes: a display panel including data lines, gate lines, and pixels, the display panel is operated in an active period or in a blank period; and a driving circuit for driving the display panel, the driving circuit including: a signal controller for outputting clock control signals; a voltage generator for receiving the clock control signals, wherein the voltage generator outputs active clock signals synchronized with the clock control signals during the active period and outputs blank clock signals during the blank period; and an overcurrent detection circuit for receiving the clock control signals and the blank clock signals, the overcurrent detection circuit detects an overcurrent of the blank clock signals, and a phase difference between the clock control signals in the active period is different from a phase difference between the clock control signals in the blank period.

Abstract: A display device to display an image during frame intervals, and to display a blank image during a blank interval defined between the frame intervals, includes: a gate driving circuit including a plurality of stages, an ith stage (i is an integer greater than or equal to 2) from among the plurality of stages including a clock terminal to receive a clock signal, wherein the clock signal swings between a first clock voltage and a second clock voltage smaller than the first clock voltage during a normal interval corresponding to each of the frame intervals, and the clock signal is changed to a voltage lower than the second clock voltage during a stabilization interval corresponding to the blank interval.

Abstract: A display device includes: a display panel including data lines, gate lines, and pixels, the display panel is operated in an active period or in a blank period; and a driving circuit for driving the display panel, the driving circuit including: a signal controller for outputting clock control signals; a voltage generator for receiving the clock control signals, wherein the voltage generator outputs active clock signals synchronized with the clock control signals during the active period and outputs blank clock signals during the blank period; and an overcurrent detection circuit for receiving the clock control signals and the blank clock signals, the overcurrent detection circuit detects an overcurrent of the blank clock signals, and a phase difference between the clock control signals in the active period is different from a phase difference between the clock control signals in the blank period.

Abstract: A display apparatus includes a first substrate, a first dummy substrate on the first substrate, and a second dummy substrate extending from the first dummy substrate and bent. The second dummy substrate is on different side surfaces of the first substrate in a first direction. The display apparatus also includes a plurality of pixels on the first dummy substrate, a gate driver on the second dummy substrate and connected to the pixels, and a data driver connected to one side of the first dummy substrate in a second direction crossing the first direction and connected to the pixels.

Abstract: A gate driving circuit includes: a plurality of stages to provide gate signals to gate lines of a display panel, a k-th stage, where k is a natural number greater than or equal to 2, from among the plurality of stages being configured: to receive a clock signal, a (k?1)th carry signal from a (k?1)th stage, a (k+1)th carry signal from a (k+1)th stage, a (k+2)th carry signal from a (k+2)th stage, a first voltage, and a second voltage, the clock signal being a pulse signal in which a high voltage and a third voltage appear periodically, and the third voltage having a lower voltage level than those of the first voltage and the second voltage; and to output a k-th gate signal and a k-th carry signal.

Abstract: A display device to display an image during frame intervals, and to display a blank image during a blank interval defined between the frame intervals, includes: a gate driving circuit including a plurality of stages, an ith stage (i is an integer greater than or equal to 2) from among the plurality of stages including a clock terminal to receive a clock signal, wherein the clock signal swings between a first clock voltage and a second clock voltage smaller than the first clock voltage during a normal interval corresponding to each of the frame intervals, and the clock signal is changed to a voltage lower than the second clock voltage during a stabilization interval corresponding to the blank interval.

Abstract: A gate driving circuit includes: a plurality of stages to provide gate signals to gate lines of a display panel, a k-th stage, where k is a natural number greater than or equal to 2, from among the plurality of stages being configured: to receive a clock signal, a (k?1)th carry signal from a (k?1)th stage, a (k+1)th carry signal from a (k+1)th stage, a (k+2)th carry signal from a (k+2)th stage, a first voltage, and a second voltage, the clock signal being a pulse signal in which a high voltage and a third voltage appear periodically, and the third voltage having a lower voltage level than those of the first voltage and the second voltage; and to output a k-th gate signal and a k-th carry signal.

Abstract: A dust core includes soft magnetic particles, a first coating layer, a second coating layer, and a third coating layer. The first coating layer is made of aluminum oxide with which at least a part of surfaces of the soft magnetic particles are coated. The second coating layer is made of aluminum nitride with which at least a part of a surface of the first coating layer is coated. The third coating layer is made of low-melting-point glass with which at least a part of a surface of the second coating layer is coated. The low-melting-point glass has a softening point lower than an annealing temperature of the soft magnetic particles.

Abstract: A gate driving circuit comprising stages cascade-connected with each other and configured to output gate signals, a stage of the stages including a pull-up circuit configured to output a high voltage of a clock signal as a high voltage of a gate signal in response to a bootstrap voltage of a control node in a period of a frame period, a first discharging circuit configured to discharge a voltage of the control node to a first low voltage in response to a carry signal of at least one stage of the plurality of stages that is subsequent to the stage, and a second discharging circuit configured to discharge a voltage of the control node to a second low voltage being lower than the first low voltage in response to a carry signal of at least one stage of the plurality of stages that is subsequent to the stage.

Abstract: A display device includes: a display panel including data lines, gate lines, and pixels, the display panel is operated in an active period or in a blank period; and a driving circuit for driving the display panel, the driving circuit including: a signal controller for outputting clock control signals; a voltage generator for receiving the clock control signals, wherein the voltage generator outputs active clock signals synchronized with the clock control signals during the active period and outputs blank clock signals during the blank period; and an overcurrent detection circuit for receiving the clock control signals and the blank clock signals, the overcurrent detection circuit detects an overcurrent of the blank clock signals, and a phase difference between the clock control signals in the active period is different from a phase difference between the clock control signals in the blank period.

Abstract: A soft magnetic member is formed such that, when a differential relative permeability in an applied magnetic field of 100 A/m is represented by a first differential relative permeability ??L, and when a differential relative permeability in an applied magnetic field of 40 kA/m is represented by a second differential relative permeability ??H, a ratio of the first differential relative permeability ??L to the second differential relative permeability ??H satisfies a relationship of ??L/??H?10, and a magnetic flux density in an applied magnetic field of 60 kA/m is 1.15 T or higher.

Abstract: A display apparatus includes a first substrate, a first dummy substrate on the first substrate, and a second dummy substrate extending from the first dummy substrate and bent. The second dummy substrate is on different side surfaces of the first substrate in a first direction. The display apparatus also includes a plurality of pixels on the first dummy substrate, a gate driver on the second dummy substrate and connected to the pixels, and a data driver connected to one side of the first dummy substrate in a second direction crossing the first direction and connected to the pixels.

Abstract: A gate driving circuit includes: a plurality of stages to provide gate signals to gate lines of a display panel, a k-th stage, where k is a natural number greater than or equal to 2, from among the plurality of stages being configured: to receive a clock signal, a (k?1)th carry signal from a (k?1)th stage, a (k+1)th carry signal from a (k+1)th stage, a (k+2)th carry signal from a (k+2)th stage, a first voltage, and a second voltage, the clock signal being a pulse signal in which a high voltage and a third voltage appear periodically, and the third voltage having a lower voltage level than those of the first voltage and the second voltage; and to output a k-th gate signal and a k-th carry signal.