Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.

Abstract: A semiconductor memory device includes a substrate including memory cell, peripheral, and intermediate regions; a device isolation pattern; a partitioning pattern; bit lines extending in a first direction to a boundary between the intermediate and peripheral regions; storage node contacts on the memory cell region and filling a lower portion of a space between bit lines; landing pads on the storage node contacts; dummy storage node contacts on the intermediate region and filling a lower portion of a space between bit lines; dummy landing pads on the dummy storage node contacts; and a dam structure on the intermediate region, extending in the first direction, and having a bar shape, wherein the dummy landing pads are spaced apart from an edge of the dam structure in a second direction, and the dummy storage node contacts are in contact with the partitioning pattern.

Abstract: A semiconductor device includes a bit line structure on a substrate, a lower contact plug on a portion of the substrate adjacent to the bit line structure, an upper contact plug including a first metal pattern on the lower contact plug and a second metal pattern contacting an upper surface and an upper sidewall of the first metal pattern, and a capacitor on the upper contact plug. The upper surface of the first metal pattern is above an upper surface of the bit line structure with respect to an upper surface of the substrate.

Abstract: A semiconductor device includes conductive patterns, an insulating pattern between the conductive patterns, an insulating etch stop layer on the conductive patterns and the insulating pattern, a capacitor including first electrodes in contact with the first conductive patterns, a second capacitor electrode, and a dielectric between the first and second capacitor electrodes, an insulating structure covering the capacitor and the insulating etch stop layer, and a peripheral contact plug through the insulating structure and the insulating etch stop layer and including first through fifth plug regions stacked on top of each other, at least a portion of a side surface of the fourth plug region having an inclination angle different from inclinations angles of the third and fifth plug regions, and a vertical thickness of the fifth plug region being at least twice as great as a sum of vertical thicknesses of the first to fourth plug regions.

Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.

Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.

Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.

Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.

Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.

Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

Abstract: A semiconductor device includes active pillars protruding from a semiconductor substrate and spaced apart from each other in a first direction and a second direction that is perpendicular to the first direction, a word line extending in the first direction between the active pillars, a drain region disposed in an upper portion of each of the active pillars, and a separation pattern provided between the word line and the drain region. A bottom surface of the separation pattern is disposed at a lower level than a bottom surface of the drain region.

Abstract: A memory device includes a substrate including active areas and isolation areas, trenches in the isolation areas, active patterns in the active areas, the active patterns protruding from the substrate, isolation layers filling the trenches, gate trenches crossing the active patterns and the isolation layers, and gate line stacks filling the gate trenches, a first width of the gate trench in the isolation layer being greater than a second width of the gate trench in the active pattern.

Abstract: A semiconductor device includes active pillars protruding from a semiconductor substrate and spaced apart from each other in a first direction and a second direction that is perpendicular to the first direction, a word line extending in the first direction between the active pillars, a drain region disposed in an upper portion of each of the active pillars, and a separation pattern provided between the word line and the drain region. A bottom surface of the separation pattern is disposed at a lower level than a bottom surface of the drain region.

Abstract: Systems, apparatuses, and methods provided for ping-pong charge pumps. Flying capacitors present in ping-pong charge pumps are operated out of phase to increase equalization periods. Out-of-phase operation also decreases voltage differences between flying capacitors during equalization periods thus decreasing ping-pong charge pump output voltage ripple and snapback. The voltages of the flying capacitors may be equalized without the use of an equalization switch. Differential control currents that are based on the voltage difference between the flying capacitors are used to enable or disable the flying capacitors from driving an output load of the ping-pong charge pump during certain phases of operation. A capacitor with a lower voltage may be disabled, thus providing for voltage equalization as the enabled capacitor sources current to the output load. The flying capacitors are also equalized during overlapping time periods in which the flying capacitors are charging.

Abstract: A semiconductor memory device includes a variable resistance memory element connected between first and second conductive lines intersecting each other, and a PN junction diode connected between the variable resistance memory element and the first conductive line. The method of operating the semiconductor device includes supplying the variable resistance memory element with a first directional current flowing from the second conductive line to the first conductive line by applying a first forward bias to the PN junction diode, and supplying the variable resistance memory element with a second directional current flowing from the first conductive line to the second conductive line by applying a reverse bias to the PN junction diode immediately after applying a second forward bias to the PN junction diode.

Abstract: Provided are data storage devices and methods of manufacturing the same. The device may include a plurality of cell selection parts formed in a substrate, a plate conductive pattern covering the cell selection parts and electrically connected to first terminals of the cell selection parts, a plurality of through-pillars penetrating the plate conductive pattern and insulated from the plate conductive pattern, and a plurality of data storage parts directly connected to the plurality of through-pillars, respectively. The data storage parts may be electrically connected to second terminals of the cell selection parts, respectively.