Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

Abstract: An apparatus for processing a substrate includes a first processing unit configured to have a first processing container having a first inner space and a first support unit supporting and rotating the substrate in the first inner space; a second processing unit configured to have a second processing container having a second inner space and a second support unit supporting and rotating the substrate in the second inner space; an exhaust unit configured to exhaust the first and the second inner space; a first exhaust pipe configured to have a first exhaust port for introducing atmosphere of the first inner space and exhaust the atmosphere introduced through the first exhaust port to the integrated duct; and a second exhaust pipe configured to have a second exhaust port for introducing atmosphere of the second inner space and exhaust the atmosphere introduced through the second exhaust port to the integrated duct.

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

Abstract: Disclosed are a substrate processing method and a substrate processing apparatus. The substrate processing method of etching a thin film formed on a substrate in units of atomic layers includes a modifying step of supplying a modifying gas to a processing space in a chamber accommodating the substrate to modify a surface of the thin film and form a modified film having a first thickness, a surface adsorption step of supplying a precursor to the processing space to adsorb the precursor to the modified surface of the thin film, and an etching step of supplying heat to the substrate adsorbed with the precursor to etch the modified surface of the thin film adsorbed with the precursor. The surface adsorption step and the etching step are repeatedly performed multiple times until the modified film having the first thickness is etched.

Abstract: Disclosed are an electrostatic precipitator system and method. The disclosed electrostatic precipitator system includes: an electrostatic precipitator; a main hopper which is disposed below the electrostatic precipitator so as to be in fluid communication with the electrostatic precipitator; a plurality of sub-hoppers disposed below the main hopper so as to be in fluid communication with the main hopper; a vertical duct disposed below each sub-hopper so as to be in fluid communication with each sub-hopper; and a water tank disposed below the vertical duct so as to be in fluid communication with the vertical duct.

Abstract: Provided is a desalination device using a solvent extraction method, comprising: a first mixing tank composed of a feed water inlet into which feed water comprising salt ions and water molecules flows, a first solvent inlet into which a first solvent selectively reacting more with the water molecules than with the salt ions flows, a first mixing tank body in which the feed water and the first solvent are mixed so as to form a mixed water, and a mixed water outlet through which the mixed water is discharged; a first separation tank composed of a mixed water inlet which communicates with the mixed water outlet so that the mixed water flows therein, a first separation tank body in which brine containing salt ions of the feed water and first treatment water formed from mixing the water molecules of the feed water and the first solvent of the mixed water are separated by layer, and a first treatment water outlet through which the first treatment water is discharged; a second mixing tank composed of a first treatme

Abstract: Disclosed are an electrostatic precipitator system and method. The disclosed electrostatic precipitator system includes: an electrostatic precipitator; a main hopper which is disposed below the electrostatic precipitator so as to be in fluid communication with the electrostatic precipitator; a plurality of sub-hoppers disposed below the main hopper so as to be in fluid communication with the main hopper; a vertical duct disposed below each sub-hopper so as to be in fluid communication with each sub-hopper; and a water tank disposed below the vertical duct so as to be in fluid communication with the vertical duct.

Abstract: A waste heat recovery system and method are disclosed. The waste heat recovery system disclosed herein comprises: a waste heat recovery boiler; a waste heat supply member configured to supply waste heat to the waste heat recovery boiler; and a water tank configured to fluidly communicate with the waste heat supply member.

Abstract: A storage device and an operating method of the storage device are provided. The storage device comprises a first non-volatile memory device, a second non-volatile memory device, a third non-volatile memory device a storage controller configured to control the first non-volatile memory device, the second non-volatile memory device, and the third non-volatile memory device, control the first non-volatile memory device to extract a first on-cell count value after a first soft erase operation, set first to third read level offsets of the respective first to third non-volatile memory devices based on the respective first to third on-cell count values, select the first to third defense code parameter sets each corresponding to the respective first to third read level offsets, and transmits first to third read commands based on the selected respective first to third defense code parameter sets to the respective first to third non-volatile memory devices.

Abstract: Disclosed is an operation method of a memory device that includes a memory block including a plurality of cell transistors stacked in a direction perpendicular to a substrate. The plurality of cell transistors may include a ground selection transistor and an erase control transistor. The erase control transistor may be between the substrate and the ground selection transistor. The operation method may include performing a first erase operation on the ground selection transistor, performing a first program operation on the erase control transistor after the first erase operation, performing a second program operation on the ground selection transistor after the first program operation, and performing a second erase operation on the erase control transistor after the second program operation.

Abstract: A waste heat recovery system and method are disclosed. The waste heat recovery system disclosed herein comprises: a waste heat recovery boiler; a waste heat supply member configured to supply waste heat to the waste heat recovery boiler; and a water tank configured to fluidly communicate with the waste heat supply member.

Abstract: An application processor and a system on chip (SoC) that incorporates the application processor are provided. The application processor includes a first core configured to process first data per unit time, a second core configured to process second data larger than the first data per unit time, and a lookup table configured to determine whether to activate the first core or the second core based on at least one of an analysis result of a message signal received by a communications processor, a sensing signal supplied to the application processor and a power level supplied to the communications processor.

Abstract: An application processor and a system on chip (SoC) that incorporates the application processor are provided. The application processor includes a first core configured to process first data per unit time, a second core configured to process second data larger than the first data per unit time, and a lookup table configured to determine whether to activate the first core or the second core based on at least one of an analysis result of a message signal received by a communications processor, a sensing signal supplied to the application processor and a power level supplied to the communications processor.

Abstract: Provided is a substrate processing apparatus which effectively exhausts organic gas, such as ammonia, generated in the process of processing a substrate by using gas. The substrate processing apparatus includes: a housing provided with a processing space in which a substrate is processed therein; a hand which transfers the substrate to the processing space; a guide located at a side portion of the housing, and which guides a vertical movement of the hand; and an exhaust duct located adjacent to the housing and the guide, and which provides an exhaust path of the processing space, and an exhaust path of an interior space of the guide.

Abstract: An operation method of a nonvolatile memory device includes performing a 1-stage program step and a 1-stage verify step on a first word line, storing a first time stamp, performing the 1-stage program step and the 1-stage verify step on a second word line, storing a second time stamp, calculating a delay time based on the first time stamp and the second time stamp, determining whether the delay time is greater than a threshold value, adjusting at least one 2-stage verify voltage associated with the first word line from a first voltage level to a second voltage level based on the delay time, and performing a 2-stage program step and a 2-stage verify step on the first word line. A level of the at least one 1-stage verify voltage is lower than the second voltage level, and the second voltage level is lower than the first voltage level.

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

Abstract: A method of operating a storage device for programming data into a flash memory before a surface mount technology (SMT) process is provided. The method includes: comparing program states of first memory cells connected to a first word line with program states of second memory cells connected to a second word line; changing the program states of the second memory cells according to a result of the comparing; and multi-bit programming the data and changed state information into the second memory cells.

Abstract: A blower unit for a vehicle and an air conditioning device including the same, the blower unit including: a scroll casing having an inlet port; a fan rotatably disposed in the scroll casing; a motor having a shaft coupled to the fan; and a bell mouth disposed in the inlet port, in which an inner end of the scroll casing, which defines the inlet port, is disposed to be spaced apart from the fan in a radial direction to define a separation space, and the bell mouth prevents air, which flows by a rotation of the fan, from flowing reversely through the separation space. The blower unit and the air conditioning device including the same prevent air from flowing reversely to the outside of the scroll casing by means of the arrangement of the bell mouth and the scroll casing and the structural shape of the bell mouth.

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

Abstract: Disclosed is an operation method of a memory device which includes a plurality of memory cells stacked in a direction perpendicular to a substrate and a plurality of word lines respectively connected with the plurality of memory cells. The method includes applying a 0-th pass voltage to a first selected word line among the plurality of word lines and applying a first pass voltage to a first upper adjacent word line among the plurality of word lines, during a first word line setup period, and applying a first program voltage to the first selected word line and applying a second pass voltage smaller than the first pass voltage to the first upper adjacent word line, during a first program execution period after the first word line setup period. The first upper adjacent word line is a word line physically adjacent to the first selected word line.