Abstract: A display device includes a light emitting element disposed on a substrate to include an emission layer; and a light controller disposed over the light emitting element, the light controller includes light blocking patterns to extend in a first direction and spaced apart in a second direction intersecting the first direction; and a transmission portion disposed between the light blocking patterns to extend in the first direction, and the transmission portion includes a first transparent organic layer; a transparent inorganic layer disposed on the first transparent organic layer; and a second transparent organic layer disposed on the transparent inorganic layer.

Abstract: A display device according to an embodiment includes a light-emitting device disposed on a substrate and including an emission layer, and a light control layer disposed on the light-emitting device. The light control layer includes a plurality of light blocking patterns extending in a first direction and spaced in a second direction intersecting the first direction, and a transmission layer disposed among the plurality of light blocking patterns and including a transparent organic layer and a transparent inorganic layer that are alternately stacked on each other.

Abstract: Provided is a binder for a secondary battery including a copolymer including repeating units of the Chemical Formula 1, Chemical Formula 2, Chemical Formula 3, and Chemical Formula 4 disclosed herein. When the binder for a secondary battery is applied to a negative electrode and a secondary battery, expansion of the negative electrode may be effectively suppressed. Furthermore, the binder for a secondary battery has improved adhesion to effectively suppress exfoliation and desorption of a negative electrode, thereby manufacturing a secondary battery having significantly improved charge/discharge cycle characteristics and battery performance by using the binder.

Abstract: An apparatus for predicting a traffic speed and a method thereof are provided. The apparatus includes an input device that receives traffic speed sequences of a plurality of links and a controller that detects a spatio-temporal relationship between traffic speeds of the plurality of links and predicts a future traffic speed of a target link based on the spatio-temporal relationship between the traffic speeds of the plurality of links.

Abstract: A display device includes a light-emitting device disposed on a substrate and including an emission layer, and a light controller disposed on the light-emitting device. The light controller includes a plurality of main light blocking patterns extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, and a plurality of sub-light blocking patterns disposed between adjacent ones of the plurality of main light blocking patterns, extending in the first direction, and spaced apart from each other in the second direction. Each of the plurality of main light blocking patterns has a first thickness in a thickness direction of the substrate, and each of the plurality of sub-light blocking patterns has a second thickness that is less than the first thickness in the thickness direction of the substrate.

Abstract: A glass stress test method includes breaking a glass, analyzing a shape of a crack of a broken portion of the glass in a plan view, finding a breakage origin of the glass based on the shape of the crack in the plan view, analyzing a cross-section of the breakage origin, and calculating a stress of the glass based on a cross-sectional analysis result of the breakage origin. The stress of the glass is calculated as a value proportional to a floor constant defined by a condition of a floor surface disposed when the glass is broken.

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

Abstract: Disclosed is an operation method of a memory device which includes a plurality of memory cells stacked in a direction perpendicular to a substrate and a plurality of word lines respectively connected with the plurality of memory cells. The method includes applying a 0-th pass voltage to a first selected word line among the plurality of word lines and applying a first pass voltage to a first upper adjacent word line among the plurality of word lines, during a first word line setup period, and applying a first program voltage to the first selected word line and applying a second pass voltage smaller than the first pass voltage to the first upper adjacent word line, during a first program execution period after the first word line setup period. The first upper adjacent word line is a word line physically adjacent to the first selected word line.

Abstract: A storage device including a nonvolatile memory device that includes a nonvolatile memory cell array including a string including first and second memory cells stacked sequentially, and an OTP memory cell array that stores reference count values, the first and second memory cells respectively connected to first and second word lines; a controller including a processor that generates a read command for the first memory cell; a read level generator including a counter that receives the read command and calculates an off-cell count value of memory cells connected to the second word line, and a comparator that receives a first reference count value from the OTP memory cell array, compares the off-cell count value with the first reference count value to determine a threshold voltage shift of the second memory cell, and determines a read level of the first memory cell based on the threshold voltage shift.

Abstract: The present disclosure relates to a display device and a manufacturing method thereof, and a display device according to one or more embodiments includes a substrate, a transistor above the substrate, a first pixel electrode connected to the transistor, a scattering layer above the first pixel electrode, and defining repeating protrusions and depressions, a second pixel electrode above the scattering layer, and connected with the first pixel electrode, an emission layer above the second pixel electrode, and a common electrode above the emission layer.

Abstract: Disclosed is a desalination apparatus using a solvent extraction scheme.

Abstract: An apparatus for treating a substrate, the apparatus comprising: a treating container having an inner space; a support unit supporting and rotating the substrate in the inner space; and an exhaust unit exhausting an air flow in the inner space, wherein the treating container includes an outer cup providing the inner space; and an inner cup disposed at the inner space and spaced apart from the outer cup, and wherein the outer cup has a protrusion at a side wall thereof.

Abstract: Disclosed is an air conditioner for a vehicle, the air conditioner having an improved guide structure capable of increasing an air volume by preventing a collision between air flowing through an upper passage and air flowing through a lower passage. The air conditioner for a vehicle comprises: an air conditioning case having an air passage formed therein and an air outlet which includes a defrost vent and a face vent; and a heat exchanger for cooling and a heat exchanger for heating, which are provided in the air passage of the air conditioning case.

Abstract: A substrate treatment apparatus is provided. The substrate treatment apparatus includes a substrate support part provided with a seating surface and configured to support a substrate, a guide ring annularly disposed along an edge of the substrate support part to surround the substrate, and a centering part provided inside the guide ring and configured to center the substrate by moving in a direction parallel to the seating surface to pressurize the edge of the substrate.

Abstract: A nonvolatile memory device includes a memory block including a first structure formed on a substrate and a second structure formed on the first structure. An erase method of the nonvolatile memory device includes applying a word line erase voltage to first normal word lines of the first structure and second normal word lines of the second structure, and applying a junction word line erase voltage smaller than the word line erase voltage to at least one of a first junction word line of the first structure and a second junction word line of the second structure. The first junction word line is a word line adjacent to the second structure from among word lines of the first structure, and the second junction word line is a word line adjacent to the first structure from among word lines of the second structure.

Abstract: Disclosed is an operation method of a memory device that includes a memory block including a plurality of cell transistors stacked in a direction perpendicular to a substrate. The plurality of cell transistors may include a ground selection transistor and an erase control transistor. The erase control transistor may be between the substrate and the ground selection transistor. The operation method may include performing a first erase operation on the ground selection transistor, performing a first program operation on the erase control transistor after the first erase operation, performing a second program operation on the ground selection transistor after the first program operation, and performing a second erase operation on the erase control transistor after the second program operation.

Abstract: A program method of a nonvolatile memory device including receiving a write address and write data, generating a seed corresponding to the write address, generating a random sequence by using the seed, randomizing the write data by using the random sequence, and programming the randomized write data to a memory area corresponding to the write address may be provided. The seed may provide state shaping variable depending on a location of a word line, at which the received write data is to be programmed.

Abstract: An operation method of a nonvolatile memory device includes performing a 1-stage program step and a 1-stage verify step on a first word line, storing a first time stamp, performing the 1-stage program step and the 1-stage verify step on a second word line, storing a second time stamp, calculating a delay time based on the first time stamp and the second time stamp, determining whether the delay time is greater than a threshold value, adjusting at least one 2-stage verify voltage associated with the first word line from a first voltage level to a second voltage level based on the delay time, and performing a 2-stage program step and a 2-stage verify step on the first word line. A level of the at least one 1-stage verify voltage is lower than the second voltage level, and the second voltage level is lower than the first voltage level.

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

Abstract: An application processor and a system on chip (SoC) that incorporates the application processor are provided. The application processor includes a first core configured to process first data per unit time, a second core configured to process second data larger than the first data per unit time, and a lookup table configured to determine whether to activate the first core or the second core based on at least one of an analysis result of a message signal received by a communications processor, a sensing signal supplied to the application processor and a power level supplied to the communications processor.