Patents by Inventor Junichi Ariyoshi

Junichi Ariyoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190267461
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. An insulating fill material layer and drain select gate electrodes are located over the alternating stack. A group of memory stack structures extends through the alternating stack, and is arranged as rows of memory stack structures. Each memory stack structure is entirely encircled laterally by a respective one of the drain select gate electrodes. The insulating fill material layer includes a drain select level isolation structure extending between neighboring rows of memory stack structures and including a pair of sidewalls containing a respective laterally alternating sequence of planar vertical sidewall portions and concave vertical sidewall portions, and a drain select level field portion adjoined to the drain select level isolation portion.
    Type: Application
    Filed: February 27, 2018
    Publication date: August 29, 2019
    Inventors: Shinsuke YADA, Xiaolong HU, Junichi ARIYOSHI
  • Patent number: 10381450
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. An insulating fill material layer and drain select gate electrodes are located over the alternating stack. A group of memory stack structures extends through the alternating stack, and is arranged as rows of memory stack structures. Each memory stack structure is entirely encircled laterally by a respective one of the drain select gate electrodes. The insulating fill material layer includes a drain select level isolation structure extending between neighboring rows of memory stack structures and including a pair of sidewalls containing a respective laterally alternating sequence of planar vertical sidewall portions and concave vertical sidewall portions, and a drain select level field portion adjoined to the drain select level isolation portion.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Shinsuke Yada, Xiaolong Hu, Junichi Ariyoshi
  • Patent number: 10347647
    Abstract: A memory device contains a stack of insulating layers and electrically conductive word line layers, at least one first drain select gate electrode located over the stack and extending through a first drain select transistor and a second drain select transistor, at least one second drain select gate electrode located between the first drain select electrode and the stack, and extending through a third drain select transistor and a fourth drain select transistor. The first drain select transistor and the third drain select transistor are located in a first NAND memory string. The second drain select transistor and the fourth drain select transistor are located in a second NAND memory string different from the first NAND memory string. The first drain select transistor has a higher threshold voltage than the second drain select transistor. The third drain select transistor has a lower threshold voltage than the fourth drain select transistor.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 9, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Naohiro Hosoda, Keisuke Shigemura, Junichi Ariyoshi, Kazuki Kajitani, Yuji Fukano
  • Publication number: 20190198515
    Abstract: A memory device contains a stack of insulating layers and electrically conductive word line layers, at least one first drain select gate electrode located over the stack and extending through a first drain select transistor and a second drain select transistor, at least one second drain select gate electrode located between the first drain select electrode and the stack, and extending through a third drain select transistor and a fourth drain select transistor. The first drain select transistor and the third drain select transistor are located in a first NAND memory string. The second drain select transistor and the fourth drain select transistor are located in a second NAND memory string different from the first NAND memory string. The first drain select transistor has a higher threshold voltage than the second drain select transistor. The third drain select transistor has a lower threshold voltage than the fourth drain select transistor.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Inventors: Naohiro HOSODA, Keisuke SHIGEMURA, Junichi ARIYOSHI, Kazuki KAJITANI, Yuji FUKANO
  • Patent number: 10256245
    Abstract: Electrical short caused by misalignment of source select level contact via structure and support pillar structures can be prevented by modifying the pattern of the support pillar structures such that the support pillar structures are omitted from the area in which source select gate contact via structures are formed. The insulating layer at the level overlying the source select level electrically conductive layer can have a sufficient thickness to prevent deformation during formation of the backside recesses. A minimum lateral separation distance between the source select level contact via structure and the support pillar structures is greater than any minimum lateral separation distance between the word line level contact via structures and the support pillar structures.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: April 9, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Junichi Ariyoshi
  • Patent number: 10242994
    Abstract: A monolithic three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, an insulating cap layer overlying the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers and overlying the insulating cap layer, memory openings extending through the second alternating stack, the insulating cap layer, and the first alternating stack, memory stack structures located within the memory openings, and annular spacers located within the insulating cap layer and laterally surrounding a respective one of the memory stack structures.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: March 26, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Takashi Inomata, Nobuo Hironaga, Junichi Ariyoshi, Tadashi Nakamura
  • Patent number: 10236286
    Abstract: A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors is made smaller than the peak impurity concentration in the extension regions, and the depth of the ballast resistors is made greater than the depth of the extension regions.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: March 19, 2019
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Katsuyoshi Matsuura, Junichi Ariyoshi
  • Patent number: 10115681
    Abstract: A semiconductor die includes a pair of first alternating stacks of first portions of insulating layers and electrically conductive layers located over a semiconductor substrate, groups of memory stack structures vertically extending through a respective one of the pair of the first alternating stacks, a pair of second alternating stacks of second portions of the insulating layers and dielectric material layers laterally adjoined to a respective one of the first alternating stacks, such that each second portion of the insulating layers is connected to a respective one of the first portions of the insulating layers, and at least one seal ring structure laterally enclosing, and laterally spaced from, the pair of first alternating stacks, and contacting at least a first sidewall of each of the pair of second alternating stacks.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 30, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Junichi Ariyoshi
  • Patent number: 10083982
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack having a memory array region and a contact region containing stepped surfaces, and memory stack structures having a semiconductor channel and a memory film extending through the memory array region of the alternating stack. The electrically conductive layers include a drain select gate electrode and word lines, where the drain select gate electrode is thicker than each of the word lines.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: September 25, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Keisuke Shigemura, Junichi Ariyoshi, Masanori Tsutsumi, Michiaki Sano, Yanli Zhang, Raghuveer S. Makala
  • Publication number: 20180261613
    Abstract: Electrical short caused by misalignment of source select level contact via structure and support pillar structures can be prevented by modifying the pattern of the support pillar structures such that the support pillar structures are omitted from the area in which source select gate contact via structures are formed. The insulating layer at the level overlying the source select level electrically conductive layer can have a sufficient thickness to prevent deformation during formation of the backside recesses. A minimum lateral separation distance between the source select level contact via structure and the support pillar structures is greater than any minimum lateral separation distance between the word line level contact via structures and the support pillar structures.
    Type: Application
    Filed: June 26, 2017
    Publication date: September 13, 2018
    Inventor: Junichi Ariyoshi
  • Publication number: 20180138194
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack having a memory array region and a contact region containing stepped surfaces, and memory stack structures having a semiconductor channel and a memory film extending through the memory array region of the alternating stack. The electrically conductive layers include a drain select gate electrode and word lines, where the drain select gate electrode is thicker than each of the word lines.
    Type: Application
    Filed: April 25, 2017
    Publication date: May 17, 2018
    Inventors: Keisuke SHIGEMURA, Junichi ARIYOSHI, Masanori TSUTSUMI, Michiaki SANO, Yanli ZHANG, Raghuveer S. MAKALA
  • Patent number: 9935097
    Abstract: A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors is made smaller than the peak impurity concentration in the extension regions, and the depth of the ballast resistors is made greater than the depth of the extension regions.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: April 3, 2018
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Katsuyoshi Matsuura, Junichi Ariyoshi
  • Publication number: 20180006049
    Abstract: A monolithic three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, an insulating cap layer overlying the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers and overlying the insulating cap layer, memory openings extending through the second alternating stack, the insulating cap layer, and the first alternating stack, memory stack structures located within the memory openings, and annular spacers located within the insulating cap layer and laterally surrounding a respective one of the memory stack structures.
    Type: Application
    Filed: September 14, 2017
    Publication date: January 4, 2018
    Inventors: Takashi INOMATA, Nobuo HIRONAGA, Junichi ARIYOSHI, Tadashi NAKAMURA
  • Patent number: 9786681
    Abstract: Memory-opening semiconductor material portions and support opening fill structures can be simultaneously formed through a first alternating stack of first insulating layers and first sacrificial material layers. Dopant species that retard or prevent etching of the material of the support opening fill structures can be implanted into an upper portion of each support opening fill structure, while memory-opening semiconductor material portions are masked from implantation. After formation of a second alternating stack and second openings therethrough, the sacrificial material of the memory-opening semiconductor material portions is removed while the support opening fill structures is not removed. Damage to the first sacrificial material layers during formation of the staircase contact region and resulting leakage paths from word lines to the substrate through support pillar structures can be avoided or reduced by not removing the support opening fill structures.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: October 10, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Junichi Ariyoshi
  • Publication number: 20170287926
    Abstract: Memory-opening semiconductor material portions and support opening fill structures can be simultaneously formed through a first alternating stack of first insulating layers and first sacrificial material layers. Dopant species that retard or prevent etching of the material of the support opening fill structures can be implanted into an upper portion of each support opening fill structure, while memory-opening semiconductor material portions are masked from implantation. After formation of a second alternating stack and second openings therethrough, the sacrificial material of the memory-opening semiconductor material portions is removed while the support opening fill structures is not removed. Damage to the first sacrificial material layers during formation of the staircase contact region and resulting leakage paths from word lines to the substrate through support pillar structures can be avoided or reduced by not removing the support opening fill structures.
    Type: Application
    Filed: June 20, 2016
    Publication date: October 5, 2017
    Inventor: Junichi Ariyoshi
  • Publication number: 20170250177
    Abstract: A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors is made smaller than the peak impurity concentration in the extension regions, and the depth of the ballast resistors is made greater than the depth of the extension regions.
    Type: Application
    Filed: May 15, 2017
    Publication date: August 31, 2017
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Katsuyoshi Matsuura, Junichi Ariyoshi
  • Patent number: 9543318
    Abstract: An alternating stack of insulator layers and spacer material layers is formed over a substrate. Stepped surfaces are formed in a contact region in which contact via structures are to be subsequently formed. An epitaxial semiconductor pedestal can be formed by a single epitaxial deposition process that is performed after formation of the stepped surfaces and prior to formation of memory openings, or a combination of a first epitaxial deposition process performed prior to formation of memory openings and a second epitaxial deposition process performed after formation of the memory openings. The epitaxial semiconductor pedestal can have a top surface that is located above a topmost surface of the alternating stack. The spacer material layers are formed as, or can be replaced with, electrically conductive layers. Backside contact via structures can be subsequently formed.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: January 10, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhenyu Lu, Daxin Mao, Koji Miyata, Junichi Ariyoshi, Johann Alsmeier, George Matamis, Wenguang Shi, Jiyin Xu, Xiaolong Hu
  • Patent number: 9524977
    Abstract: Resistance of a semiconductor channel in three-dimensional memory stack structures can be reduced by forming a metal-semiconductor alloy region between a vertical semiconductor channel and a horizontal semiconductor channel located within a substrate. The metal-semiconductor alloy region can be formed by recessing a portion of the semiconductor material layer in the semiconductor substrate underneath a memory opening after formation of a memory film, selectively depositing a metallic material in the recess region, depositing a vertical semiconductor channel, and reacting the deposited metallic material with an adjacent portion of the semiconductor material layer and the vertical semiconductor channel. A sacrificial dielectric material layer can be formed on the memory film prior to the selective deposition of the metallic material.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: December 20, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Sateesh Koka, Tomohiro Kubo, Junichi Ariyoshi, George Matamis
  • Publication number: 20160307908
    Abstract: Resistance of a semiconductor channel in three-dimensional memory stack structures can be reduced by forming a metal-semiconductor alloy region between a vertical semiconductor channel and a horizontal semiconductor channel located within a substrate. The metal-semiconductor alloy region can be formed by recessing a portion of the semiconductor material layer in the semiconductor substrate underneath a memory opening after formation of a memory film, selectively depositing a metallic material in the recess region, depositing a vertical semiconductor channel, and reacting the deposited metallic material with an adjacent portion of the semiconductor material layer and the vertical semiconductor channel. A sacrificial dielectric material layer can be formed on the memory film prior to the selective deposition of the metallic material.
    Type: Application
    Filed: April 15, 2015
    Publication date: October 20, 2016
    Inventors: Rahul SHARANGPANI, Raghuveer S. MAKALA, Sateesh KOKA, Tomohiro KUBO, Junichi ARIYOSHI, George MATAMIS
  • Patent number: 9437598
    Abstract: A semiconductor device manufacturing method includes: forming a first well of the first conductivity type in a substrate; forming a second well of the first conductivity type in a first region of the substrate; forming a third well of the second conductivity type underneath the second well in the first region of the substrate in a position overlapping with the first well located underneath the second well in the first region of the substrate; forming a fourth well, that surrounds the second well and has the second conductivity type, in the first region of the substrate; forming a fifth well of the first conductivity type above the first well in the second region of the substrate; and forming a sixth well of the second conductivity type above the first well in the second region of the substrate.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: September 6, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Hiroyuki Ogawa, Junichi Ariyoshi