Patents by Inventor Junichi Ariyoshi

Junichi Ariyoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9437598
    Abstract: A semiconductor device manufacturing method includes: forming a first well of the first conductivity type in a substrate; forming a second well of the first conductivity type in a first region of the substrate; forming a third well of the second conductivity type underneath the second well in the first region of the substrate in a position overlapping with the first well located underneath the second well in the first region of the substrate; forming a fourth well, that surrounds the second well and has the second conductivity type, in the first region of the substrate; forming a fifth well of the first conductivity type above the first well in the second region of the substrate; and forming a sixth well of the second conductivity type above the first well in the second region of the substrate.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: September 6, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Hiroyuki Ogawa, Junichi Ariyoshi
  • Publication number: 20150200191
    Abstract: A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors is made smaller than the peak impurity concentration in the extension regions, and the depth of the ballast resistors is made greater than the depth of the extension regions.
    Type: Application
    Filed: January 12, 2015
    Publication date: July 16, 2015
    Inventors: Katsuyoshi Matsuura, Junichi Ariyoshi
  • Publication number: 20150123187
    Abstract: A semiconductor device manufacturing method includes: forming a first well of the first conductivity type in a substrate; forming a second well of the first conductivity type in a first region of the substrate; forming a third well of the second conductivity type underneath the second well in the first region of the substrate in a position overlapping with the first well located underneath the second well in the first region of the substrate; forming a fourth well, that surrounds the second well and has the second conductivity type, in the first region of the substrate; forming a fifth well of the first conductivity type above the first well in the second region of the substrate; and forming a sixth well of the second conductivity type above the first well in the second region of the substrate.
    Type: Application
    Filed: October 30, 2014
    Publication date: May 7, 2015
    Inventors: Hiroyuki Ogawa, Junichi Ariyoshi
  • Patent number: 8907430
    Abstract: A semiconductor device includes a memory transistor including a first side wall insulating film and a second side wall insulating film disposed on the outside; a high-voltage transistor including a third side wall insulating film having the same composition as that of the first side wall insulating film, and a fourth side wall insulating film having the same composition as that of the second side wall insulating film, the fourth side wall insulating film being disposed on the outside; and a low-voltage transistor including a fifth side wall insulating film having the same composition as that of the second and fourth side wall insulating films. The memory transistor, the high-voltage transistor, and the low-voltage transistor are disposed on the same substrate. A total side wall spacer width of the low-voltage transistor is smaller than that of the high-voltage transistor by a thickness corresponding to the third side wall insulating film.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: December 9, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Akihiro Usujima, Junichi Ariyoshi, Taiji Ema
  • Publication number: 20140291807
    Abstract: A semiconductor device includes a substrate, a first well of a first conductivity type formed within the substrate, a second well of a second conductivity type formed underneath the first well within the substrate and a third well of the second conductivity type formed horizontally to the first well within the substrate, and including a first region formed to a first depth from a surface of the substrate, and a second region formed to a second depth greater than the first depth from the surface of the substrate and connected to the second well.
    Type: Application
    Filed: March 12, 2014
    Publication date: October 2, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Junichi Ariyoshi
  • Patent number: 8741727
    Abstract: A method of manufacturing a semiconductor device includes forming a flash memory cell in a first region, forming a first electrode of a capacitor in a second region, forming a first silicon oxide film, a silicon nitride film, and a second silicon oxide film in this order as a second insulating film, removing the silicon nitride film and the second silicon oxide film in a partial region of the first electrode, wet-etching a first insulating film and the second insulating film in the third region, forming a second electrode of the capacitor, and etching and removing the first silicon oxide film in the partial region.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: June 3, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Junichi Ariyoshi, Taiji Ema, Toru Anezaki
  • Patent number: 8518795
    Abstract: A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: August 27, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Jusuke Ogura, Hikaru Kokura, Hideyuki Kojima, Toru Anezaki, Hiroyuki Ogawa, Junichi Ariyoshi
  • Patent number: 8470677
    Abstract: Gate electrodes are formed in a high speed transistor forming region, a low leakage transistor forming region, and a medium voltage transistor forming region, respectively. Thereafter, a photoresist film covering the medium voltage transistor forming region is formed. Then, ions of an impurity are implanted into a semiconductor substrate while using the photoresist film and the gate electrodes as a mask, and p-type pocket regions, extension regions, and impurity regions are thereby formed. Subsequently, another photoresist film covering the high speed transistor forming region is formed. Then, ions of an impurity are implanted into the semiconductor substrate while using the other photoresist film and the gate electrodes as a mask, and impurity regions and extension regions are thereby formed.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: June 25, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Junichi Ariyoshi
  • Patent number: 8435861
    Abstract: A method of manufacturing a semiconductor device includes oxidizing a surface of a semiconductor substrate to form a first insulating film covering a first area, a second area, and a third area of the semiconductor substrate; removing the portions of the first insulating film lying on the first area and the second area; oxidizing the surface of the semiconductor substrate to form a second insulating film covering the first area and the second area and further oxidizing the third area covered with the first insulating film; and removing the portion of the second insulating film lying on from the second area and the portion of the first insulating film lying on the third area.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: May 7, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Junichi Ariyoshi, Kazutaka Yoshizawa
  • Patent number: 8415215
    Abstract: A method of manufacturing a semiconductor device includes: forming first to third gate electrodes in first to third regions, respectively; forming a first mask pattern covering the second region while exposing the first and third regions; forming p-type source drain extensions and p-type pocket regions by ion implantation using the first mask pattern as a mask; forming n-type source drain extensions by ion implantation using the first mask pattern as a mask; forming a second mask pattern covering the first and third regions while exposing the second region; and forming p-type pocket regions by implanting ions of indium into the silicon substrate with the second mask pattern being used as a mask.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: April 9, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Junichi Ariyoshi, Taiji Ema
  • Publication number: 20120214283
    Abstract: Gate electrodes are formed in a high speed transistor forming region, a low leakage transistor forming region, and a medium voltage transistor forming region, respectively. Thereafter, a photoresist film covering the medium voltage transistor forming region is formed. Then, ions of an impurity are implanted into a semiconductor substrate while using the photoresist film and the gate electrodes as a mask, and p-type pocket regions, extension regions, and impurity regions are thereby formed. Subsequently, another photoresist film covering the high speed transistor forming region is formed. Then, ions of an impurity are implanted into the semiconductor substrate while using the other photoresist film and the gate electrodes as a mask, and impurity regions and extension regions are thereby formed.
    Type: Application
    Filed: December 6, 2011
    Publication date: August 23, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Junichi ARIYOSHI
  • Patent number: 8247290
    Abstract: A method of manufacturing a semiconductor device has forming a first conductive film over a semiconductor substrate, etching the first conductive film, forming a plurality of first conductive patterns arranged in a first direction, and forming a side surface on an outside of a conductive pattern positioned at an end among the plurality of first conductive patterns such that the side surface has a first inclination angle smaller than a second inclination angle of a side surface on an inside of the conductive pattern positioned at the end, forming a first insulation film over the plurality of first conductive patterns, and forming a second conductive pattern over the first insulation film.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: August 21, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Junichi Ariyoshi, Toru Anezaki, Hiroshi Morioka
  • Publication number: 20120208342
    Abstract: A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching.
    Type: Application
    Filed: April 25, 2012
    Publication date: August 16, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Jusuke OGURA, Hikaru KOKURA, Hideyuki KOJIMA, Toru ANEZAKI, Hiroyuki OGAWA, Junichi ARIYOSHI
  • Patent number: 8173514
    Abstract: A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching.
    Type: Grant
    Filed: February 12, 2009
    Date of Patent: May 8, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Jusuke Ogura, Hikaru Kokura, Hideyuki Kojima, Toru Anezaki, Hiroyuki Ogawa, Junichi Ariyoshi
  • Publication number: 20120045875
    Abstract: A method of manufacturing a semiconductor device includes: forming first to third gate electrodes in first to third regions, respectively; forming a first mask pattern covering the second region while exposing the first and third regions; forming p-type source drain extensions and p-type pocket regions by ion implantation using the first mask pattern as a mask; forming n-type source drain extensions by ion implantation using the first mask pattern as a mask; forming a second mask pattern covering the first and third regions while exposing the second region; and forming p-type pocket regions by implanting ions of indium into the silicon substrate with the second mask pattern being used as a mask.
    Type: Application
    Filed: May 19, 2011
    Publication date: February 23, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Junichi Ariyoshi, Taiji Ema
  • Publication number: 20120034751
    Abstract: A method of manufacturing a semiconductor device includes forming a flash memory cell in a first region, forming a first electrode of a capacitor in a second region, forming a first silicon oxide film, a silicon nitride film, and a second silicon oxide film in this order as a second insulating film, removing the silicon nitride film and the second silicon oxide film in a partial region of the first electrode, wet-etching a first insulating film and the second insulating film in the third region, forming a second electrode of the capacitor, and etching and removing the first silicon oxide film in the partial region.
    Type: Application
    Filed: May 12, 2011
    Publication date: February 9, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Junichi Ariyoshi, Taiji Ema, Toru Anezaki
  • Publication number: 20110136306
    Abstract: A method of manufacturing a semiconductor device includes oxidizing a surface of a semiconductor substrate to form a first insulating film covering a first area, a second area, and a third area of the semiconductor substrate; removing the portions of the first insulating film lying on the first area and the second area; oxidizing the surface of the semiconductor substrate to form a second insulating film covering the first area and the second area and further oxidizing the third area covered with the first insulating film; and removing the portion of the second insulating film lying on from the second area and the portion of the first insulating film lying on the third area.
    Type: Application
    Filed: December 1, 2010
    Publication date: June 9, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Junichi ARIYOSHI, Kazutaka Yoshizawa
  • Publication number: 20100308397
    Abstract: A method for manufacturing a semiconductor device includes forming an insulating film on a semiconductor region of a semiconductor substrate on which a MOS transistor is to be formed and patterning the insulating film; implanting an impurity into the semiconductor region through the patterned insulating film using a step of implanting an impurity into a source/drain region of the MOS transistor, to form, below the insulating film, a resistive layer of a resistance element to be formed in the semiconductor region; and siliciding a surface of the source/drain region of the MOS transistor using the insulating film as a silicidation-preventing film of the resistive layer.
    Type: Application
    Filed: June 2, 2010
    Publication date: December 9, 2010
    Applicant: Fujitsu Semiconductor Limited
    Inventor: Junichi Ariyoshi
  • Publication number: 20100308420
    Abstract: A semiconductor device includes a memory transistor including a first side wall insulating film and a second side wall insulating film disposed on the outside; a high-voltage transistor including a third side wall insulating film having the same composition as that of the first side wall insulating film, and a fourth side wall insulating film having the same composition as that of the second side wall insulating film, the fourth side wall insulating film being disposed on the outside; and a low-voltage transistor including a fifth side wall insulating film having the same composition as that of the second and fourth side wall insulating films. The memory transistor, the high-voltage transistor, and the low-voltage transistor are disposed on the same substrate. A total side wall spacer width of the low-voltage transistor is smaller than that of the high-voltage transistor by a thickness corresponding to the third side wall insulating film.
    Type: Application
    Filed: July 31, 2007
    Publication date: December 9, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Akihiro Usujima, Junichi Ariyoshi, Taiji Ema
  • Patent number: 7723825
    Abstract: According to the present invention, provided is a semiconductor device including: a p-type silicon substrate; a shallow n-well formed in the silicon substrate; a shallow p-well formed beside the shallow n-well in the silicon substrate; and a deep n-well which is formed beside the shallow p-well in the silicon substrate, and which is deeper than the shallow p-well. In addition, a deep p-well, which is deeper than the shallow p-well, is formed between the shallow p-well and the deep n-well in the silicon substrate.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: May 25, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Taiji Ema, Masayoshi Asano, Toru Anezaki, Junichi Ariyoshi