Patents by Inventor Junichi Ariyoshi

Junichi Ariyoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090215243
    Abstract: A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching.
    Type: Application
    Filed: February 12, 2009
    Publication date: August 27, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Jusuke Ogura, Hikaru Kokura, Hideyuki Kojima, Toru Anezaki, Hiroyuki Ogawa, Junichi Ariyoshi
  • Publication number: 20090001425
    Abstract: A method of manufacturing a semiconductor device has forming a first conductive film over a semiconductor substrate, etching the first conductive film, forming a plurality of first conductive patterns arranged in a first direction, and forming a side surface on an outside of a conductive pattern positioned at an end among the plurality of first conductive patterns such that the side surface has a first inclination angle smaller than a second inclination angle of a side surface on an inside of the conductive pattern positioned at the end, forming a first insulation film over the plurality of first conductive patterns, and forming a second conductive pattern over the first insulation film.
    Type: Application
    Filed: June 27, 2008
    Publication date: January 1, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Junichi Ariyoshi, Toru Anezaki, Hiroshi Morioka
  • Patent number: 7400013
    Abstract: According to one exemplary embodiment, a method includes forming first, second, and third shallow trench isolation regions in a substrate, wherein the second shallow trench isolation region is situated between the first and the third shallow trench isolation regions. The second shallow trench isolation region is removed to form a transistor channel trench. A substantially U-shaped gate is formed in the transistor channel trench. According to another embodiment, a transistor includes a substrate, and first and second shallow trench isolation regions in the substrate. A substantially U-shaped gate is formed in the substrate between said first and second shallow trench isolation regions.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: July 15, 2008
    Assignee: Spansion LLC
    Inventor: Junichi Ariyoshi
  • Publication number: 20080001258
    Abstract: According to the present invention, provided is a semiconductor device including: a p-type silicon substrate; a shallow n-well formed in the silicon substrate; a shallow p-well formed beside the shallow n-well in the silicon substrate; and a deep n-well which is formed beside the shallow p-well in the silicon substrate, and which is deeper than the shallow p-well. In addition, a deep p-well, which is deeper than the shallow p-well, is formed between the shallow p-well and the deep n-well in the silicon substrate.
    Type: Application
    Filed: October 30, 2006
    Publication date: January 3, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Taiji Ema, Masayoshi Asano, Toru Anezaki, Junichi Ariyoshi
  • Patent number: 7157336
    Abstract: The method of manufacturing a semiconductor device comprises the steps of: forming a gate electrode on a semiconductor substrate through a gate insulated film; forming source/drain regions to be adjacent to the gate electrode forming an Al wiring through an interlayer insulating film covering the gate electrode; and implanting impurity ions into a surface of the semiconductor substrate using as a mask the Al wiring and a photoresist formed thereon, thereby writing information into each of elements constituting a mask ROM and changing an outputting manner at an output port.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: January 2, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Junji Yamada, Yutaka Yamada, Junichi Ariyoshi
  • Publication number: 20060226515
    Abstract: A semiconductor device includes: a gate electrode on a semiconductor substrate through a gate insulated film; source/drain regions to be adjacent to said gate electrode; and an Al wiring through an interlayer insulating film covering said gate electrode, wherein impurity ions are implanted into a surface of said semiconductor substrate using as a mask said Al wiring, and a protection film is formed on the Al wiring so that the Al wiring is not exposed when said interlayer insulating film is etched.
    Type: Application
    Filed: June 13, 2006
    Publication date: October 12, 2006
    Inventors: Junji Yamada, Yutaka Yamada, Junichi Ariyoshi
  • Patent number: 7084463
    Abstract: A semiconductor device includes: a gate electrode on a semiconductor substrate through a gate insulated film; source/drain regions to be adjacent to said gate electrode; and an Al wiring through an interlayer insulating film covering said gate electrode, wherein impurity ions are implanted into a surface of said semiconductor substrate using as a mask said Al wiring, and a protection film is formed on the Al wiring so that the Al wiring is not exposed when said interlayer insulating film is etched.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: August 1, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Junji Yamada, Yutaka Yamada, Junichi Ariyoshi
  • Patent number: 6830978
    Abstract: On a semiconductor substrate having a gate electrode and an LDD layer formed thereon, an SiN film to be a silicide block is formed. An opening communicating with the LDD layer is provided for the SiN film. Impurities are introduced into the LDD layer through the opening to form a source/drain layer, and the surface thereof is silicided to form a silicide film. Next, an interlayer insulation film of SiO2 is formed and then etched under a condition of an etching rate of SiO2 higher than that of SiN to form a contact hole reaching the LDD layer from the upper surface of the interlayer insulation film via the opening.
    Type: Grant
    Filed: August 20, 2003
    Date of Patent: December 14, 2004
    Assignee: Fujitsu Limited
    Inventors: Junichi Ariyoshi, Satoshi Torii
  • Publication number: 20040155297
    Abstract: On a semiconductor substrate having a gate electrode and an LDD layer formed thereon, an SiN film to be a silicide block is formed. An opening communicating with the LDD layer is provided for the SiN film. Impurities are introduced into the LDD layer through the opening to form a source/drain layer, and the surface thereof is silicided to form a silicide film. Next, an interlayer insulation film of SiO2 is formed and then etched under a condition of an etching rate of SiO2 higher than that of SiN to form a contact hole reaching the LDD layer from the upper surface of the interlayer insulation film via the opening.
    Type: Application
    Filed: August 20, 2003
    Publication date: August 12, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Junichi Ariyoshi, Satoshi Torii
  • Patent number: 6576518
    Abstract: Disclosed is a method of manufacturing a semiconductor device including a gate electrode on a semiconductor substrate through a gate insulated film; source/drain regions formed to be adjacent to the gate electrode; and an Al wiring formed through an interlayer insulating film covering the gate electrode, wherein impurity ions are implanted in a surface layer of the substrate using the Al wiring and a photoresist formed thereon as a mask, and wherein no photoresist is formed on the Al wiring arranged above regions in which the impurity ions are implanted in adjacent elements.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: June 10, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Junji Yamada, Yutaka Yamada, Junichi Ariyoshi
  • Publication number: 20020173103
    Abstract: The method of manufacturing a semiconductor device comprises the steps of: forming a gate electrode on a semiconductor substrate through a gate insulated film; forming source/drain regions to be adjacent to the gate electrode forming an Al wiring through an interlayer insulating film covering the gate electrode; and implanting impurity ions into a surface of the semiconductor substrate using as a mask the Al wiring and a photoresist formed thereon, thereby writing information into each of elements constituting a mask ROM and changing an outputting manner at an output port.
    Type: Application
    Filed: March 13, 2002
    Publication date: November 21, 2002
    Inventors: Junji Yamada, Yutaka Yamada, Junichi Ariyoshi
  • Publication number: 20020130423
    Abstract: A semiconductor device includes: a gate electrode on a semiconductor substrate through a gate insulated film; source/drain regions to be adjacent to said gate electrode; and an Al wiring through an interlayer insulating film covering said gate electrode, wherein impurity ions are implanted into a surface of said semiconductor substrate using as a mask said Al wiring, and a protection film is formed on the Al wiring so that the Al wiring is not exposed when said interlayer insulating film is etched.
    Type: Application
    Filed: March 11, 2002
    Publication date: September 19, 2002
    Inventors: Junji Yamada, Yutaka Yamada, Junichi Ariyoshi