Patents by Inventor Junichi Hayashi
Junichi Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11655360Abstract: A gas-barrier resin (A) having an oxygen permeability coefficient of 1.0×10?14 (cm3·cm/cm2·s·Pa) or less; and a copolymer (B) containing monomer structural units represented by the formula (1), the formula (2), and the formula (3): where: R1 represents a hydrogen atom or a methyl group; R2 represents a hydrocarbon group having 1 to 20 carbon atoms that may be substituted with a halogen atom, a hydroxy group, an alkoxy group, or an amino group; 1, m, and n represent numerical values representing molar proportions of the respective monomer structural units, and n may represent 0; and p represents an integer of from 1 to 4, wherein a ratio of a mass of the copolymer (B) to a total mass of the gas-barrier resin (A) and the copolymer (B) is from 1 mass % to 40 mass %.Type: GrantFiled: July 17, 2018Date of Patent: May 23, 2023Assignees: SHOWA DENKO K.K., JAPAN POLYETHYLENE CORPORATIONInventors: Junichi Kuroda, Yoshikuni Okumura, Shinya Hayashi, Masahiro Uematsu, Takaaki Hattori, Yuichiro Yasukawa
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Patent number: 10482256Abstract: An information processing apparatus holding a secure chip includes a determination unit that determines whether the information processing apparatus returns from an idle state; a detection unit that, if the determination unit determines that the information processing apparatus returns from the idle state, detects initialization of the secure chip before starting application software; and a control unit that, if the detection unit detects the initialization of the secure chip, controls an operation of the information processing apparatus so that a hash value of the application software is not registered in the secure chip that is initialized.Type: GrantFiled: March 28, 2016Date of Patent: November 19, 2019Assignee: Canon Kabushiki KaishaInventors: Junichi Hayashi, Koji Harada, Nobuhiro Tagashira, Takami Eguchi, Yasuhiro Nakamoto, Kazuya Kishi, Ayuta Kawazu
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Patent number: 10346179Abstract: An information processing apparatus having a function of entering and returning from a hibernation state and communicable with a server apparatus performing device certification includes a storage unit configured to, in a case where a software module is activated, store a hash value of the activated software module in a volatile memory, a request unit configured to request device certification based on a hash value stored in the volatile memory from the server apparatus, and an excluding unit configured to, in a case where the device certification is requested after returning from the hibernation state, exclude a software module activated before entering the hibernation state from a target of the device certification.Type: GrantFiled: November 19, 2015Date of Patent: July 9, 2019Assignee: Canon Kabushiki KaishaInventors: Kazuya Kishi, Koji Harada, Junichi Hayashi, Nobuhiro Tagashira, Takami Eguchi, Yasuhiro Nakamoto, Ayuta Kawazu
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Patent number: 9597767Abstract: A polishing media is formed of a sintered body in which a metal structure and a ceramic structure are intermingled with each other. The polishing media is preferably produced by molding a mixed powder of a metal powder and a ceramic powder by an injection molding method and sintering the resulting molded article. Further, the ceramic structure is preferably formed of aluminum oxide, and the metal structure is preferably formed of tungsten.Type: GrantFiled: March 29, 2012Date of Patent: March 21, 2017Assignee: Seiko Epson CorporationInventors: Hideki Ishigami, Hidefumi Nakamura, Junichi Hayashi
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Publication number: 20160292422Abstract: An information processing apparatus holding a secure chip includes a determination unit that determines whether the information processing apparatus returns from an idle state; a detection unit that, if the determination unit determines that the information processing apparatus returns from the idle state, detects initialization of the secure chip before starting application software; and a control unit that, if the detection unit detects the initialization of the secure chip, controls an operation of the information processing apparatus so that a hash value of the application software is not registered in the secure chip that is initialized.Type: ApplicationFiled: March 28, 2016Publication date: October 6, 2016Inventors: Junichi Hayashi, Koji Harada, Nobuhiro Tagashira, Takami Eguchi, Yasuhiro Nakamoto, Kazuya Kishi, Ayuta Kawazu
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Patent number: 9378775Abstract: Such a device is disclosed that includes first and second chips stacked to each other, and a third chip controlling the first and second chips, stacked on the first and second chips, and including first, second and third output circuits. The first output circuit supplies a first command signal to the first chip. The second output circuit supplies the first command signal to the second chip. The third output circuit supplies a second command signal to the first and second chips.Type: GrantFiled: January 25, 2012Date of Patent: June 28, 2016Assignee: PS4 LUXCO S.A.R.L.Inventors: Junichi Hayashi, Homare Sato
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Publication number: 20160147542Abstract: An information processing apparatus having a function of entering and returning from a hibernation state and communicable with a server apparatus performing device certification includes a storage unit configured to, in a case where a software module is activated, store a hash value of the activated software module in a volatile memory, a request unit configured to request device certification based on a hash value stored in the volatile memory from the server apparatus, and an excluding unit configured to, in a case where the device certification is requested after returning from the hibernation state, exclude a software module activated before entering the hibernation state from a target of the device certification.Type: ApplicationFiled: November 19, 2015Publication date: May 26, 2016Inventors: Kazuya Kishi, Koji Harada, Junichi Hayashi, Nobuhiro Tagashira, Takami Eguchi, Yasuhiro Nakamoto, Ayuta Kawazu
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Publication number: 20150243347Abstract: To prevent a multiword state in which a plurality of word lines are active in a same memory bank, the semiconductor device includes a plurality of memory chips commonly receiving an access command, in which each of the plurality of memory chips are provided with a control circuit ignoring an new access command when the bank address information in the new access command is the same as the bank address information for the specified memory bank even if the new access command received before reading/writing data from/to the specified memory bank of the selected memory chip is completed contains chip selection information selecting another memory chip.Type: ApplicationFiled: August 20, 2013Publication date: August 27, 2015Inventor: Junichi Hayashi
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Patent number: 9077914Abstract: This invention can generate printed matter on which a multi-valued discrimination image of three values or more cannot be visually confirmed under ordinary light but can be visually confirmed via an infrared camera under infrared light. To this end, a holding unit holds items of color information C1, C2, and C3 each indicating usage amounts of printing materials of three types, used by a printing apparatus, which have a color difference under visible light not more than a pre-set threshold, and which have different infrared light ray absorption rates. When a latent image generating unit generates infrared light ray latent image data of three tones, a discrimination image data generating unit decides one color information item Ci (1?i?3) held by the holding unit, and outputs the decided Ci to an output unit which outputs the received pixel values to the printing apparatus.Type: GrantFiled: October 19, 2011Date of Patent: July 7, 2015Assignee: CANON KABUSHIKI KAISHAInventors: Koji Harada, Junichi Hayashi, Masanori Yokoi
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Patent number: 8961178Abstract: A dental implant comprises a titanium member composed of a sintered body made from titanium or titanium alloy; and a ceramic member composed of oxide-based ceramic, and the ceramic member fixed to the titanium member. The titanium member has a recess, and the ceramic member has a protrusion coupled to the recess and pores, and the titanium member covers the protrusion of the ceramic member. The protrusion has a cross-sectional area increasing portion whose cross-sectional area increases toward a dead-end portion of the recess in a direction away from a base end of the protrusion. The titanium member is firmly fixed and joined to the ceramic member in a state that a part of the titanium or the titanium alloy is penetrated into the pores of the protrusion of the ceramic member.Type: GrantFiled: October 11, 2012Date of Patent: February 24, 2015Assignee: Seiko Epson CorporationInventors: Junichi Hayashi, Michio Ito
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Patent number: 8922839Abstract: A array including array elements in a number smaller than the minimum number of pixels, having values larger than Th_c, and a plurality of array elements having values smaller than Th_c is generated. A formation array having the same size as that of a latent image is generated from the generated array. An image obtained by replacing the pixel value at a pixel position within the first region in the latent image with the value at the pixel position in the formation array is generated as a configuration image. The pixel value at each pixel position in the configuration image, that corresponds to each pixel position in the input image, is output as the amount of a highly infrared absorbent color material used to print a pixel at this pixel position in the input image.Type: GrantFiled: August 6, 2012Date of Patent: December 30, 2014Assignee: Canon Kabushiki KaishaInventors: Masanori Yokoi, Koji Harada, Junichi Hayashi
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Publication number: 20140376321Abstract: To include a plurality of core chips to which different pieces of chip information from each other are given in advance. A first refresh command is divided into a plurality of second refresh commands having different timings from each other, and a refresh operation is performed on a core chip for which a count value of the second refresh commands and at least a portion of the chip information match each other. With this configuration, even when the second refresh command is commonly supplied to a plurality of core chips, it is possible to shift a timing for the refresh operation in each of the core chips. Therefore, it is possible to reduce a peak current at the time of the refresh operation.Type: ApplicationFiled: September 8, 2014Publication date: December 25, 2014Inventors: Homare Sato, Junichi Hayashi
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Patent number: 8885430Abstract: To include a plurality of core chips to which different pieces of chip information from each other are given in advance. A first refresh command is divided into a plurality of second refresh commands having different timings from each other, and a refresh operation is performed on a core chip for which a count value of the second refresh commands and at least a portion of the chip information match each other. With this configuration, even when the second refresh command is commonly supplied to a plurality of core chips, it is possible to shift a timing for the refresh operation in each of the core chips. Therefore, it is possible to reduce a peak current at the time of the refresh operation.Type: GrantFiled: October 7, 2010Date of Patent: November 11, 2014Assignee: PS4 Luxco S.A.R.L.Inventors: Homare Sato, Junichi Hayashi
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Publication number: 20140247684Abstract: A semiconductor device includes: an interface chip including a read timing control circuit that outputs, in response to a command signal and a clock signal supplied from the outside, a plurality of read control signals that are each in synchronization with the clock signal and have different timings; and core chips including a plurality of internal circuits that are stacked on the interface chip and each perform an operation indicated by the command signal in synchronization with the read control signals. According to the present invention, it is unnecessary to control latency in the core chips and therefore to supply the clock signal to the core chips.Type: ApplicationFiled: May 16, 2014Publication date: September 4, 2014Inventor: Junichi Hayashi
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Patent number: 8782897Abstract: A dental implant for preventing elution of metal when applied within an oral cavity and preventing the occurrence of mismatching (bumpy occlusion or the like) when fixed in place, and its manufacturing method are provided. The abutment is manufactured through steps including molding a titanium molded body composition to obtain a titanium molded body, molding a ceramic molded body composition to obtain a ceramic molded body, assembling the titanium molded body and the ceramic molded body together to obtain an assembled body, degreasing the assembled body so that the titanium molded body becomes a titanium degreased body and the ceramic molded body becomes a ceramic degreased body, and sintering the assembled body to transform the titanium degreased body into a titanium member and to transform the ceramic degreased body into a ceramic member so that the titanium member and the ceramic member are firmly fixed and joined together.Type: GrantFiled: March 4, 2013Date of Patent: July 22, 2014Assignee: Seiko Epson CorporationInventors: Junichi Hayashi, Michio Ito
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Publication number: 20140177367Abstract: A device includes a plurality of Dynamic Random Access Memory (DRAM) chips in a stacked configuration connected by through silicon vias (TSVs), and each of the plurality of DRAM chips being configured to provide a local bank active signal to indicate when any one of a plurality of banks on a respective one of the plurality of DRAM chips is active, and local bank active signals from the plurality of DRAM chips being supplied through TSVs of intervening ones of the plurality of DRAM chips to a lowermost one of the plurality of DRAM chips.Type: ApplicationFiled: February 25, 2014Publication date: June 26, 2014Inventor: Junichi HAYASHI
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Patent number: 8737160Abstract: A semiconductor device includes: an interface chip including a read timing control circuit that outputs, in response to a command signal and a clock signal supplied from the outside, a plurality of read control signals that are each in synchronization with the clock signal and have different timings; and core chips including a plurality of internal circuits that are stacked on the interface chip and each perform an operation indicated by the command signal in synchronization with the read control signals. According to the present invention, it is unnecessary to control latency in the core chips and therefore to supply the clock signal to the core chips.Type: GrantFiled: October 20, 2011Date of Patent: May 27, 2014Inventor: Junichi Hayashi
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Patent number: 8718409Abstract: In verification of image data of a captured image as to whether it is original one, the verification is possible even for image data subjected to a peripheral illumination correction or an exposure correction. An order information calculation unit selects a pixel set including two or more pixels based on pixel values and information on an image space of image data of a captured image, and calculates an order of magnitude between pixels in the selected pixel set. A verification data producing unit generates verification data used in verification of whether the image data has not been tampered with, based on the calculated order of magnitude. An image output unit outputs the image data and the verification data.Type: GrantFiled: October 28, 2010Date of Patent: May 6, 2014Assignee: Canon Kabushiki KaishaInventors: Junichi Hayashi, Nobuhiro Tagashira, Kazuya Kishi, Yasuhiro Nakamoto, Yoshiharu Imamoto, Jun Tamaru
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Publication number: 20140100094Abstract: A tool magazine that can make a long tool reasonably coexist with other tools and a machining center with the tool magazine are provided. The tool magazine has a rotatable magazine main body and plural of tool holders installed on the magazine main body. Each of the tool holders moves to a tool exchange position sequentially. A part or all of the tool holders has a capability of changing between an exchange posture that holds the tool in parallel to a rotation shaft of the magazine main body and a transport posture that holds the tool along with a plane perpendicular to the rotation shaft of the magazine main body. The tool holder capable of changing postures takes the exchange posture when it locates in the tool exchange position and takes the transport posture when it leave the exchange position. The machining center has the above tool magazine.Type: ApplicationFiled: December 12, 2013Publication date: April 10, 2014Applicant: Komatsu NTC Ltd.Inventors: Junichi HAYASHI, Fumihiro KAMIKONYA, Yasuo HASEGAWA
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Patent number: 8693277Abstract: Such a device is disclosed that includes a first chip outputting a bank address signal and an active signal, and a plurality of second chips stacked on the first chip. Each of the second chips includes a plurality of memory banks each selected based on the bank address signal. Selected one or ones of the memory banks is brought into an active state in response to the active signal. Each of the second chips activates a local bank active signal when at least one of the memory banks included therein is in the active state. The first chip activates a bank active signal when at least one of the local bank active signals is activated.Type: GrantFiled: January 10, 2012Date of Patent: April 8, 2014Assignee: Elpida Memory, Inc.Inventor: Junichi Hayashi