Abstract: An integrated circuit device includes a driver macrocell in which a plurality of circuit blocks are integrated into a macrocell. The driver macrocell includes a data driver block DB for driving data lines, a memory block MB which stores image data, and a pad block PDB in which pads for electrically connecting output lines of the data driver block DB with the data lines are disposed. The data driver block DB and the memory block MB are disposed along a direction D1, and the pad block PDB is disposed on the D2 side of the data driver block DB and the memory block MB.

Abstract: An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include a high-speed interface circuit block HB which transfers data through a serial bus using differential signals, and a circuit block other than HB. The high-speed interface circuit block HB is disposed as an Mth circuit block CBM (2?M?N?1) of the circuit blocks CB1 to CBN.

Abstract: An integrated circuit device includes a RAM block including a plurality of wordlines WL, a plurality of bitlines BL, a plurality of memory cells MC, wordline control circuit, and a data read control circuit, and a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block. The data read control circuit reads data for pixels corresponding to the signal lines by N (N is an integer larger than one) times reading in one horizontal scan period 1H of the display panel. The data line driver block includes first to N-th divided data line driver blocks, each of which drives a different data line group of the data line groups and is disposed along a first direction X in which the bitlines BL extend.

Abstract: An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include at least one memory block MB which stores image data, and at least one data driver block DB which drives data lines. The memory block MB and the data driver block DB are disposed adjacent to each other along the first direction D1.

Abstract: An integrated circuit device includes: first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The first to Nth circuit blocks CB1 to CBN includes a logic circuit block LB which sets grayscale characteristic adjustment data; and a grayscale voltage generation circuit block GB which generates grayscale voltages based on the set adjustment data. The logic circuit block LB and the grayscale voltage generation circuit block GB are disposed adjacent to each other along the direction D1.

Abstract: An integrated circuit device, including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include at least one memory block MB which stores image data, and at least one data driver block DB which drives data lines; and the memory block MB includes a memory cell array, a row address decoder RD, and a sense amplifier block SAB.

Abstract: An integrated circuit device includes first to Nth circuit blocks CB1 to CBN disposed along a direction D1 when a direction from a first side which is a short side of the integrated circuit device toward a third side opposite to the first side is a direction D1 and a direction from a second side which is a long side of the integrated circuit device toward a fourth side opposite to the second side is a direction D2. At least one of the circuit blocks on both ends of the circuit blocks CB1 to CBN is a scan driver block for driving a scan line. Or, the scan driver block SB is disposed along the direction D1 on the side of the first to Nth circuit blocks in the direction D2.

Abstract: A display device comprising: a display panel including a plurality of scan lines and a plurality of data lines; and an integrated circuit device including a display memory which stores data for at least one frame displayed in the display panel. The display memory (or RAM block) includes a plurality of wordlines, a plurality of bitlines, and a plurality of memory cells. The integrated circuit device has a side parallel to the scan lines of the display panel, and the bitlines of the display memory extend in a first direction parallel to the side.

Abstract: An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include a logic circuit block LB, a grayscale voltage generation circuit block GB, data driver blocks DB1 to DB4, and a power supply circuit block PB. The data driver blocks DB1 to DB4 are disposed between the logic circuit block LB and the grayscale voltage generation circuit block GB, and the power supply circuit block PB.

Abstract: An integrated circuit device includes: first to Nth circuit blocks CB1 to CBN disposed along a direction D1, the circuit blocks CB1 to CBN includes a data driver block DB. A data driver DR included in the data driver block DB includes Q driver cells DRC1 to DRCQ arranged along a direction D2, each of the driver cells outputting a data signal corresponding to image data for one pixel. When a width of each of the driver cells DRC1 to DRCQ in the direction D2 is WD, each of the circuit blocks CB1 to CBN has a width WB in the direction D2 of “Q×WD?WB<(Q+1)×WD”.

Abstract: An integrated circuit device includes: a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block. The data line driver block includes first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line groups. The wordline control circuit drives an identical wordline N times from among the wordlines in one horizontal scan period of the display panel. The first to Nth divided data line drivers are disposed along a first direction in which the bitlines extend.

Abstract: An integrated circuit device includes first and second transistors NTr1 and PTr1 push-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node ND by a charge-pump operation, and a pad PD electrically connected with the connection node ND and electrically connected with a flying capacitor, to which a given voltage is applied at one end, at the other end of the flying capacitor. The pad PD is disposed in an upper layer of at least one of the first and second transistors NTr1 and PTr1 so that the pad PD overlaps part or the entirety of at least one of the first and second transistors NTr1 and PTr1.

Abstract: An integrated circuit device has a display memory which stores data for at least one frame displayed in a display panel which has a plurality of scan lines and a plurality of data lines. The display memory includes a plurality of RAM blocks, each of the RAM blocks including a plurality of wordlines WL, a plurality of bitlines BL, a plurality of memory cells MC, and a data read control circuit. Each of the RAM blocks is disposed along a first direction X in which the bitlines BL extend.

Abstract: An integrated circuit device includes a scan driver block SB which generates a control signal for driving a scan line, a pad PDt electrically connected with the scan line, and transistors pDTrt and nDTrt of which a connection node DNDt is electrically connected with the PDt pad and which are push-pull connected between a high-potential-side power supply and a low-potential-side power supply. The transistors pDTrt and nDTrt are gate-controlled based on the control signal from the scan driver block SB. The pad PDt is disposed in an upper layer of at least one of the transistors pDTrt and nDTrt so that the pad PDt overlaps part or the entirety of at least one of the transistors pDTrt and nDTrt.

Abstract: A method of manufacturing a ferroelectric film includes crystallizing a raw material having a complex oxide, the method including: performing a heat treatment in a first condition in which a predetermined pressure and a predetermined temperature are applied; and maintaining a second condition, in which a pressure and a temperature lower than the pressure and the temperature in the first condition are applied, after the heat treatment in the first condition, and the raw material is crystallized by repeating the heat treatment in the first condition and the maintaining the second condition.

Abstract: A method of reading data in a ferroelectric memory device includes applying a read voltage to a ferroelectric capacitor, and detecting a voltage that reflects an amount of a dynamic change in capacitance of the ferroelectric capacitor to which the read voltage is applied. Since a voltage difference ?V occurs at a time T between the case where the polarization of a memory cell which has stored first data is not reversed and the case where the polarization of a memory cell which has stored second data is reversed, a read margin increases.

Abstract: To provide a nondestructive-read ferroelectric memory capable of realizing high speed, high integration, and long service life. The present invention is provided with an MFSFET 100 having a ferroelectric thin film at its gate portion, word line 104, bit line 105, and bit line 106 so as to apply voltage equal to or higher than the coercive electric field of the ferroelectric thin film between the bit line 105 and the word line 104 at first write timing and apply voltage equal to or higher than the coercive electric field between the bit line 106 and the word line 104 at second write timing, and applies voltage equal to or lower than the coercive electric field of the ferroelectric thin film between the bit line 105 and the word line 104 at first read timing to detect the current flowing between the both bit lines, and applies voltage equal to or lower than the coercive electric field between the bit line 106 and the word line 104 at second read timing to detect the current flowing between the both bit lines.

Abstract: In the manufacture of an integrated circuit, a first electrode (48) is formed on a substrate (28). In a first embodiment, a strontium bismuth tantalate layer (50) and a second electrode (52) are formed on top of the first electrode (48). Prior to the final crystallization anneal, the first electrode (48), the strontium bismuth tantalate layer (50) and the second electrode (52) are patterned. The final crystallization anneal is then performed on the substrate (28). In a second embodiment, a second layer (132) of strontium bismuth tantalate is deposited on top of the strontium bismuth tantalate layer (50) prior to the forming of the second electrode (52) on top of the first and second layers (50), (132). In a third embodiment, a carefully controlled UV baking process is performed on the strontium bismuth tantalate layer (50).

Abstract: A ferroelectric memory includes a memory cell array in which memory cells having a ferroelectric capacitor are arranged in a matrix shape. The memory cell array includes a ferroelectric layer formed out of a thin film made of a Bi layer-structured ferroelectric single crystal having a (001) orientation and which is patterned such that the ferroelectric layer has two or more side walls perpendicular to a (100) axis of the Bi layer-structured ferroelectrics, first electrodes contacting at least one of the side walls of the ferroelectric layer and which are formed in stripe patterns extending along the one side wall, and second electrodes which contact the other side wall of the ferroelectric layer not contacting the first electrodes and which are formed in stripe patterns to intersect the first electrodes. The memory cells are formed at intersections between the first electrodes and the second electrodes.

Abstract: A ferroelectric memory device includes a simple matrix type memory cell array. Provided that the maximum absolute value of a voltage applied between a first signal electrode and a second signal electrode is Vs, polarization P of a ferroelectric capacitor formed of the first electrode, the second electrode, and ferroelectric layer is within the range of 0.1P(+Vs)<P(?1/3Vs) when the applied voltage is changed from +Vs to ?1/3Vs, and 0.1P(?Vs)>P(+1/3Vs) when the applied voltage is changed from ?Vs to +1/3Vs.