Abstract: A semiconductor device is provided with an SRAM memory cell. The semiconductor device includes a first gate-gate electrode layer, a second gate-gate electrode layer, a first drain-drain wiring layer, a second drain-drain wiring layer, a first drain-gate wiring layer and second drain-gate wiring layers. The first drain-gate wiring layer and an upper layer and a lower layer of the second drain-gate wiring layer are located in different layers, respectively. A first protruded active region is provided in a manner to protrude from an end portion of the first active region.

Abstract: A ferroelectric layer including space charges. The space charges show a concentration peak at least at one of an upper portion and a lower portion of the ferroelectric layer in a direction of the thickness of the ferroelectric layer.

Abstract: A method of manufacturing a ferroelectric film includes crystallizing a raw material having a complex oxide, the method including: performing a heat treatment in a first condition in which a predetermined pressure and a predetermined temperature are applied; and maintaining a second condition, in which a pressure and a temperature lower than the pressure and the temperature in the first condition are applied, after the heat treatment in the first condition, and the raw material is crystallized by repeating the heat treatment in the first condition and the maintaining the second condition.

Abstract: A ferroelectric material for forming a ferroelectric that is described by a general formula ABO3, includes an A-site compensation component which compensates for a vacancy of an A site, and a B-site compensation component which compensates for a vacancy of a B site.

Abstract: A method of reading data in a ferroelectric memory device includes applying a read voltage to a ferroelectric capacitor, and detecting a voltage that reflects an amount of a dynamic change in capacitance of the ferroelectric capacitor to which the read voltage is applied. Since a voltage difference &Dgr;V occurs at a time T between the case where the polarization of a memory cell which has stored first data is not reversed and the case where the polarization of a memory cell which has stored second data is reversed, a read margin increases.

Abstract: A semiconductor device is provided with a memory cell. The semiconductor device includes a first gate-gate electrode layer, a second gate-gate electrode layer, a first drain-drain wiring layer, a second drain-drain wiring layer, a first drain-gate wiring layer and a second drain-gate wiring layer. The first drain-gate wiring layer and an upper layer and a lower layer of the second drain-gate wiring layer are located in different layers, respectively.

Abstract: A semiconductor memory device has a peripheral circuit area and a memory cell area on a main surface thereof. The semiconductor memory device includes a first well formed in the peripheral circuit area, a second well of a first conductivity type formed in the memory cell area, a third well of a second conductivity type formed in the memory cell area, and a device isolation structure formed in the memory cell area for isolating an element formed in the second well from an element formed in the third well. The second well of the first conductivity type has a depth shallower than a depth of the first well. The third well of the second conductivity type is equal in depth to the second well. The second and third wells are formed down to a level lower than the device isolation structure.

Abstract: A semiconductor memory device has a plurality of sub power source lines for supplying a power source voltage to memory cells, a main power source line for supplying the power source voltage to the sub power source lines, and a plurality of fuse elements for connecting the main power source line to the sub power source lines. Predetermined number of the sub power source lines are commonly connected by one of plurality of common connecting sections. Each of the common connecting sections is disposed at one ends of the sub power source lines. Each of the common connecting sections is connected to the main power source line through each of the fuse elements. The number of the sub power source lines connected to the common connecting section is equal to the number of the sub word lines subordinate to one main word line, and also equal to the number of the redundant sub word lines subordinate to one redundant main word line.

Abstract: In the manufacture of an integrated circuit memory cell, a strontium bismuth tantalate or strontium bismuth tantalum niobate thin film layer (50) is deposited on a substrate (28, 49) and a carefully controlled UV baking process is performed on the strontium bismuth tantalate layer (50) prior to the deposition of an ultra-thin bismuth tantalate layer (51). A second electrode (52) is formed on top of the ultra-thin bismuth tantalate layer (51).

Abstract: A semiconductor device having a memory cell including first and second load transistors, first and second driver transistors, and first and second transfer transistors. The semiconductor device includes first and second gate—gate electrode layers, first and second drain—drain wiring layers, and first and second drain-gate wiring layers. The first drain-gate wiring layer and the second drain-gate wiring layer are located in different layers. The first drain-gate wiring layer is located below the first drain—drain wiring layer, and the second drain-gate wiring layer is located in above the first drain—drain wiring layer. This structure provides a semiconductor device that has reduced cell area. The invention also provides a memory system and electronic apparatus that include the above semiconductor device.

Abstract: Semiconductor devices are provided that include a memory cell having load transistors, driver transistors, and transfer transistors. The semiconductor device has a first element-forming region that can be provided in, for example, a p-well region. The first element-forming region can include includes a first active region, a second active region, a third active region, a fourth active region and a fifth active region. The third active region, the fourth active region and the fifth active region can be provided between the first active region and the second active region. The first active region and the second active region can be continuous with the third active region, the fourth active region and the fifth active region, respectively. Thus, semiconductor devices can be provided having element-forming regions that can be readily formed. Memory systems and electronic equipment that include such semiconductor devices can also be provided.

Abstract: A semiconductor device is provided with a memory cell. The semiconductor device includes a first gate—gate electrode layer, a second gate—gate electrode layer, a first drain—drain wiring layer, a second drain—drain wiring layer, a first drain-gate wiring layer and second drain-gate wiring layers. The first drain-gate wiring layer and an upper layer and a lower layer of the second drain-gate wiring layer are located in different layers, respectively. The width of the first gate—gate electrode layer in the first load transistor is larger than the width of the first gate—gate electrode layer in the first driver transistor.

Abstract: In the manufacture of an integrated circuit, a first electrode (48) is formed on a substrate (28). In a first embodiment, a strontium bismuth tantalate layer (50) and a second electrode (52) are formed on top of the first electrode (48). Prior to the final crystallization anneal, the first electrode (48), the strontium bismuth tantalate layer (50) and the second electrode (52) are patterned. The final crystallization anneal is then performed on the substrate (28). In a second embodiment, a second layer (132) of strontium bismuth tantalate is deposited on top of the strontium bismuth tantalate layer (50) prior to the forming of the second electrode (52) on top of the first and second layers (50), (132). In a third embodiment, a carefully controlled UV baking process is performed on the strontium bismuth tantalate layer (50).

Abstract: A ferroelectric memory device includes a simple matrix type memory cell array. Provided that the maximum absolute value of a voltage applied between a first signal electrode and a second signal electrode is Vs, polarization P of a ferroelectric capacitor formed of the first signal electrode, the second signal electrode, and ferroelectric layer is within the range of 0.1P(+Vs)<P(−⅓Vs) when the applied voltage is changed from +Vs to −⅓Vs, and 0.1P(−Vs)>P(+⅓Vs) when the applied voltage is changed from −Vs to +⅓Vs.

Abstract: A ferroelectric memory device includes a simple matrix type memory cell array. Provided that the maximum absolute value of a voltage applied between a first signal electrode and a second signal electrode is Vs, polarization P of a ferroelectric capacitor formed of the first electrode, the second electrode, and ferroelectric layer is within the range of 0.1P(+Vs)<P(−1/3Vs) when the applied voltage is changed from +Vs to −1/3Vs, and 0.1P(−Vs)>P(+1/3Vs) when the applied voltage is changed from −Vs to +1/3Vs.

Abstract: A semiconductor device having a memory cell including first and second load transistors, first and second driver transistors, and first and second transfer transistors. The semiconductor device includes a first gate-gate electrode layer and a first drain-gate wiring layer. A distance L1 between the edges of the first drain-gate wiring layer and an active region of the first driver transistor is greater than or equal to a distance L2 between the first drain-gate wiring layer and an active region of the first load transistor. This structure provides semiconductor devices in which memory cells having desired characteristics can be readily fabricated. The invention also provides memory systems and electronic apparatuses which include the above semiconductor devices.

Abstract: The present invention provides a semiconductor device including a first gate—gate electrode layer located in a first conductive layer and including gate electrodes of a first load transistor and a first driver transistor and a second gate—gate electrode layer located in the first conductive layer and including gate electrodes of a second load transistor and a second driver transistor. A first drain—drain connecting layer is located in a second conductive layer which is an upper layer of the first conductive layer and connects a drain of the first load transistor with a drain of the first driver transistor. A second drain—drain connecting layer is located in the second conductive layer and connects a drain of the second load transistor with a drain of the second driver transistor.

Abstract: A semiconductor memory device has a plurality of sub power source lines for supplying a power source voltage to memory cells, a main power source line for supplying the power source voltage to the sub power source lines, and a plurality of fuse elements for connecting the main power source line to the sub power source lines. Predetermined number of the sub power source lines are commonly connected by one of plurality of common connecting sections. Each of the common connecting sections is disposed at one ends of the sub power source lines. Each of the common connecting sections is connected to the main power source line through each of the fuse elements. The number of the sub power source lines connected to the common connecting section is equal to the number of the sub word lines subordinate to one main word line, and also equal to the number of the redundant sub word lines subordinate to one redundant main word line.

Abstract: A semiconductor memory device (SRAM) comprises memory cells, each of which includes two load transistors, two driver transistors and two transfer transistors. The SRAM cell includes a semiconductor substrate in which the transistors are formed, a first interlayer dielectric formed on the semiconductor substrate, first contact portions formed in the first interlayer dielectric and first wiring layers (node wiring layers and pad layers) formed on the first interlayer dielectric. The first contact portions and the first wiring layers include metal layers made of refractory metal and a refractory metal nitride layers. This semiconductor memory device of the present invention is capable of enhancing an integration degree of wiring layers and achieving a microfabrication.

Abstract: A semiconductor substrate has a main surface, a well, a plurality of memory cells, a first memory cell region, a second memory cell region, a border region, a well contact region, a first dummy element, a second dummy element, a first transistor and a second transistor. The first and second memory cell regions are located over the well. The memory cells are formed in the first and second memory cell regions. The border region is located over the well on a border between the first memory cell region and the second memory cell region. The well contact region is formed in the well in the border region and is electrically connected to a wiring layer for fixing the voltage of the well. The first and second dummy elements are formed in the border. The first transistor, that is a component of the memory cell, is formed in the first memory cell region and is located adjacent to the first dummy element.