Patents by Inventor Junichi Kasai

Junichi Kasai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6090301
    Abstract: A method for fabricating a bump forming plate member by which bumps can be formed on an electronic component. A mask is formed on a surface of a crystalline plate, and the crystalline plate is subjected to anisotropic etching to form a plurality of grooves. The crystalline plate is also subjected to isotropic etching to deepen the grooves. The method can further includes additional anisotropic and isotropic etchings. Also, a method for fabricating a metallic bump forming plate member is disclosed. This method uses the above described crystalline plate having the grooves, and includes fabrication of a replica using the crystalline plate as an original, and fabrication of a metallic bump forming plate member using the replica as an original.
    Type: Grant
    Filed: May 19, 1997
    Date of Patent: July 18, 2000
    Assignee: Fujitsu Limited
    Inventors: Masataka Mizukoshi, Ichiro Yamaguchi, Masahiro Yoshikawa, Koki Otake, Junichi Kasai
  • Patent number: 6072239
    Abstract: A device includes a chip, and a resin package sealing the chip, the resin package having resin projections located on a mount-side surface of the resin package. Metallic films are respectively provided to the resin projections. Connecting parts electrically connect electrode pads of the chip and the metallic films.
    Type: Grant
    Filed: November 6, 1996
    Date of Patent: June 6, 2000
    Assignee: Fujitsu Limited
    Inventors: Yoshiyuki Yoneda, Kazuto Tsuji, Seiichi Orimo, Hideharu Sakoda, Ryuji Nomoto, Masanori Onodera, Junichi Kasai
  • Patent number: 6034428
    Abstract: A semiconductor device includes a semiconductor chip, and a multi-layered member connected to the semiconductor chip. The multi-layered member includes one or a plurality of wiring layers and one or a plurality of insulating layers alternately stacked. The one or the plurality of insulating layers have holes. The multi-layered member has electrode parts which include deformed portions of the above one or the plurality of wiring layers obtained by deforming the above one or the plurality of wiring layers via said holes.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: March 7, 2000
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Toshimi Kawahara, Hiroyuki Ishiguro, Mitsunada Osawa, Shinichirou Taniguchi, Mayumi Osumi, Shinya Nakaseko, Yoshitugu Katoh, Junichi Kasai
  • Patent number: 6025258
    Abstract: A method for fabricating solder bumps onto a semiconductor chip. A solder ball forming member having a flat surface and a plurality of cavities arranged on the flat surface in a predetermined pattern is prepared. The cavities are then filled with a solder paste, and the solder ball forming member is heated to a temperature higher than the melting point of the solder so that the molten solder powder in the solder paste form solder balls due to surface tension. The semiconductor chip is then moved toward the solder ball forming member to transfer the heated solder balls from the solder ball forming member to the semiconductor chip.
    Type: Grant
    Filed: August 17, 1995
    Date of Patent: February 15, 2000
    Assignee: Fujitsu Limited
    Inventors: Masayuki Ochiai, Hidefumi Ueda, Michio Sono, Ichiro Yamaguchi, Kazuhiko Mitobe, Koki Otake, Junichi Kasai, Nobuo Kamehara, Yasuo Yamagishi, Masataka Mizukoshi
  • Patent number: 6025650
    Abstract: This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device comprises a semiconductor chip having a plurality of pads, a resin portion sealing said semiconductor chip and a terminal portion in which a prescribed number of pole terminals electrically connected to said pads provided in said semiconductor chip are provided, said pole terminals being exposed from said resin portion. According to the invention, a cost for production is reduced and a reliability and electrical characteristics can be improved.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: February 15, 2000
    Assignee: Fujitsu Limited
    Inventors: Kazuto Tsuji, Yoshiyuki Yoneda, Hideharu Sakoda, Ryuuji Nomoto, Eiji Watanabe, Seiichi Orimo, Masanori Onodera, Junichi Kasai
  • Patent number: 6022759
    Abstract: A semiconductor device includes a semiconductor element, a semiconductor device base member having an element mounting portion on which the semiconductor element is mounted, external connection terminals provided on the semiconductor device base member and electrically connected to the semiconductor element, and a resin sealing the semiconductor element. The semiconductor device base member includes a base part and lead parts supported by the base part. The lead parts are electrically connected to the external connection terminals. The semiconductor device base member has bent portions in which the lead parts are located on outer sides of the semiconductor device base member. The bent portions are located in edge portions of the semiconductor device base member.
    Type: Grant
    Filed: February 18, 1998
    Date of Patent: February 8, 2000
    Assignees: Fujitsu Limited, Fujitsu Automation Limited
    Inventors: Masaaki Seki, Michio Sono, Ichiro Yamaguchi, Kazuhiko Mitobe, Lim Cheang Hai, Koki Otake, Susumu Abe, Junichi Kasai, Masao Sakuma, Yoshimi Suzuki, Yasuhiro Shinma
  • Patent number: 5889333
    Abstract: A semiconductor device includes a device body including at least an LSI chip, and a lead structure having a base which is flexible and a plurality of pins which project from both sides of the base. The lead structure is integrated with the device body so that first ends of the plurality of pins are electrically connected to the LSI chip. The semiconductor device is manufactured in accordance with two steps of forming the lead structure and of integrating the lead structure with the deice body so that the first ends of the plurality of pins are electrically connected to the LSI chip.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: March 30, 1999
    Assignee: Fujitsu Limited
    Inventors: Masashi Takenaka, Junichi Kasai, Masataka Mizukoshi, Taturou Yamashita
  • Patent number: 5861669
    Abstract: A semiconductor device having a package of a single in-line type includes a semiconductor chip, a package body that accommodates the semiconductor chip therein and defined by a pair of opposing major surfaces and a plurality of interconnection leads held by the package body to extend substantially perpendicularly to a bottom surface. Each of the interconnection leads consists of an inner lead part located inside the package body and an outer lead part located outside the package body, the outer lead part being bent laterally at a boundary between the inner part and the outer part, in one of first and second directions that are opposite from each other and substantially perpendicular to the opposing major surfaces of the package body. A plurality of support legs extend laterally at the bottom surface of the package body for supporting the package body upright when the semiconductor device is placed on a substrate.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: January 19, 1999
    Assignee: Fujitsu Limited
    Inventors: Michio Sono, Junichi Kasai, Masanori Yoshimoto, Kazuto Tsuji, Kouji Saito
  • Patent number: 5842628
    Abstract: A wire bonding method includes a first bonding process for forming a first ball-shaped part in a wire and bonding the first ball-shaped part to a first connected member; a ball-shaped part forming process for guiding the wire away from a position where the wire is bonded to an inner lead so as to form a predetermined loop, and forming a second ball-shaped part in a predetermined position in the wire; and a second bonding process for bonding the second ball-shaped part to a semiconductor element pad that serves as a second connected member.
    Type: Grant
    Filed: April 8, 1996
    Date of Patent: December 1, 1998
    Assignee: Fujitsu Limited
    Inventors: Ryuji Nomoto, Kazuto Tsuji, Mitsutaka Sato, Junichi Kasai
  • Patent number: 5831332
    Abstract: A semiconductor device having a package of a single in-line type includes a semiconductor chip, a package body that accommodates the semiconductor chip therein and defined by a pair of opposing major surfaces and a plurality of interconnection leads held by the package body to extend substantially perpendicularly to a bottom surface. Each of the interconnection leads consists of an inner lead part located inside the package body and an outer lead part located outside the package body, the outer lead part being bent laterally at a boundary between the inner part and the outer part, in one of first and second directions that are opposite from each other and substantially perpendicular to the opposing major surfaces of the package body. A plurality of support legs extend laterally at the bottom surface of the package body for supporting the package body upright when the semiconductor device is placed on a substrate.
    Type: Grant
    Filed: October 29, 1996
    Date of Patent: November 3, 1998
    Assignee: Fujitsu Limited
    Inventors: Michio Sono, Junichi Kasai, Masanori Yoshimoto, Kazuto Tsuji, Kouji Saito
  • Patent number: 5804467
    Abstract: A semiconductor device includes a substrate having top and bottom surfaces, a semiconductor element mounted on the top surface of the substrate, and a resin package made of a resin and encapsulating the semiconductor element. The substrate includes at least one resin gate hole enabling the resin to be introduced from the bottom surface of the substrate via the resin gate hole when encapsulating the semiconductor element by the resin.
    Type: Grant
    Filed: May 13, 1997
    Date of Patent: September 8, 1998
    Assignees: Fujistsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Toshimi Kawahara, Shinya Nakaseko, Mitsunada Osawa, Shinichirou Taniguchi, Mayumi Osumi, Hiroyuki Ishiguro, Yoshitugu Katoh, Junichi Kasai
  • Patent number: 5801439
    Abstract: A semiconductor device includes a semiconductor element, a package sealing the semiconductor element, and leads for passing signals between the semiconductor element and an external device. Each of the leads has an inner-lead part sealed within the package and connected with the semiconductor element, and an outer-lead part which extends outward from the package toward a top of the package, and is to be connected to the external device. The outer-lead part includes a first-port part at a lower side of the package, and a second-port part at an upper side of the package.
    Type: Grant
    Filed: February 21, 1997
    Date of Patent: September 1, 1998
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Fujisawa, Mitsutaka Sato, Junichi Kasai, Masataka Mizukoshi, Kosuke Otokita, Hiroshi Yoshimura, Katsuhiro Hayashida, Akira Takashima, Masahiko Ishiguri, Michio Sono
  • Patent number: 5786985
    Abstract: A semiconductor device is adapted to be mounted on a circuit substrate in an approximate vertical position. The semiconductor device includes a semiconductor chip, a stage having a first surface and a second surface opposite to the first surface, where the semiconductor chip is mounted on the first surface, a resin package encapsulating the semiconductor chip, where the resin package has upper and lower surfaces and side surfaces, a plurality of leads respectively having one end electrically connected to the semiconductor chip and another end extending downwardly from the lower surface of the resin package, and an upper extension, provided on the stage, extending upwardly from the upper surface of the resin package.
    Type: Grant
    Filed: November 15, 1996
    Date of Patent: July 28, 1998
    Assignee: Fujitsu Limited
    Inventors: Norio Taniguchi, Junichi Kasai, Kazuto Tsuji, Michio Sono, Masanori Yoshimoto, Katsuhiro Hayashida, Mitsutaka Sato, Hiroshi Yoshimura, Tadashi Uno, Kosuke Otokita, Tetsuya Fujisawa
  • Patent number: 5773313
    Abstract: A semiconductor device includes a semiconductor chip (11) having a top surface and a bottom surface, a plurality of leads (14) arranged under the bottom surface of the semiconductor chip (11), where the leads (14) have first ends (14a) electrically coupled to the semiconductor chip (11) and second ends which form external terminals (16) and each of the external terminals have a bottom surface, and a package (17, 31) encapsulating the semiconductor chip (11) and the leads (14) so that the bottom surface of each of the external terminals (16) is exposed at a bottom surface (17a, 31a) of the package (17, 31) and remaining portions of the leads (14) are embedded within the package (17, 31), where the package (17, 31) has a size which is approximately the same as that of the semiconductor chip (11) in a plan view viewed from above the top surface of the semiconductor chip (11).
    Type: Grant
    Filed: October 24, 1995
    Date of Patent: June 30, 1998
    Assignee: Fujitsu Limited
    Inventors: Mitsutaka Sato, Junichi Kasai
  • Patent number: 5760471
    Abstract: A semiconductor device including a semiconductor element, and leads connected with the semiconductor element. Each of the leads includes an outer lead part for being connected externally. The semiconductor device further includes a plastic package sealing the semiconductor element and the leads. In the semiconductor device, the outer lead part is exposed to the outside of a side face of the plastic package, and the plastic package is mounted on any base in a standing form by the side face contacting the base.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: June 2, 1998
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Fujisawa, Mitsutaka Sato, Junichi Kasai, Masataka Mizukoshi, Kousuke Otokita, Hiroshi Yoshimura, Katsuhiro Hayashida, Akira Takashima, Masahiko Ishiguri, Michio Sono
  • Patent number: 5750421
    Abstract: A semiconductor device including a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package. The package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package.
    Type: Grant
    Filed: January 27, 1997
    Date of Patent: May 12, 1998
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited, Fujitsu Automation Limited
    Inventors: Junichi Kasai, Kazuto Tsuji, Norio Taniguchi, Takashi Mashiko, Masao Sakuma, Yukio Saigo, Yoshiyuki Yoneda, Masashi Takenaka
  • Patent number: 5747874
    Abstract: A semiconductor device includes a semiconductor element, a semiconductor device base member having an element mounting portion on which the semiconductor element is mounted, external connection terminals provided on the semiconductor device base member and electrically connected to the semiconductor element, and a resin sealing the semiconductor element. The semiconductor device base member includes a base part and lead parts supported by the base part. The lead parts are electrically connected to the external connection terminals. The semiconductor device base member has bent portions in which the lead parts are located on outer sides of the semiconductor device base member. The bent portions are located in edge portions of the semiconductor device base member.
    Type: Grant
    Filed: September 18, 1995
    Date of Patent: May 5, 1998
    Assignees: Fujitsu Limited, Fujitsu Automation Limited
    Inventors: Masaaki Seki, Michio Sono, Ichiro Yamaguchi, Kazuhiko Mitobe, Lim Cheang Hai, Koki Otake, Susumu Abe, Junichi Kasai, Masao Sakuma, Yoshimi Suzuki, Yasuhiro Shinma
  • Patent number: 5736428
    Abstract: A process for manufacturing semiconductor device including a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package. The package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package.
    Type: Grant
    Filed: January 27, 1997
    Date of Patent: April 7, 1998
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited, Fujitsu Automation Limited
    Inventors: Junichi Kasai, Kazuto Tsuji, Norio Taniguchi, Takashi Mashiko, Masao Sakuma, Yukio Saigo, Yoshiyuki Yoneda, Masashi Takenaka
  • Patent number: 5684675
    Abstract: A semiconductor device unit includes a holder having a plurality of holding parts, and a plurality of semiconductor devices held by the holding parts of the holder. Each of the semiconductor devices has a generally parallelepiped shape with top and bottom surfaces and at least one side surface provided with leads which are exposed whereby the semiconductor device unit stands by itself on the leads.
    Type: Grant
    Filed: June 1, 1994
    Date of Patent: November 4, 1997
    Assignee: Fujitsu, Ltd.
    Inventors: Norio Taniguchi, Junichi Kasai, Kazuto Tsuji, Michio Sono, Masanori Yoshimoto
  • Patent number: 5679978
    Abstract: A semiconductor device includes a substrate having top and bottom surfaces, a semiconductor element mounted on the top surface of the substrate, and a resin package made of a resin and encapsulating the semiconductor element. The substrate includes at least one resin gate hole enabling the resin to be introduced from the bottom surface of the substrate via the resin gate hole when encapsulating the semiconductor element by the resin.
    Type: Grant
    Filed: October 24, 1994
    Date of Patent: October 21, 1997
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Toshimi Kawahara, Shinya Nakaseko, Mitsunada Osawa, Shinichirou Taniguchi, Mayumi Osumi, Hiroyuki Ishiguro, Yoshitugu Katoh, Junichi Kasai