Patents by Inventor Junichi Nagata

Junichi Nagata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080090095
    Abstract: The present invention provides adhesiveless copper clad laminates, which does not have defects on a copper film part due to a pin hole generated at the time of forming a base metal layer on an insulating film by dry plating process, has excellent adhesion between the insulating film and the base metal layer and corrosion resistance, and has a copper film layer having high insulation reliability, and provides a method for manufacturing such adhesiveless copper clad laminates. In adhesiveless copper clad laminates according to the present invention provided by forming a base metal layer directly at least on one plane of an insulating film without having an adhesive in between, and then by forming a copper film layer on the base metal layer, the base metal layer having a film thickness of 3 to 50 nm is formed by dry plating method and mainly contains a chrome-molybdenum-nickel alloy wherein the chrome ratio is 4 to 22 weight %, the molybdenum ratio is 5 to 40 weight %, and the balance is nickel.
    Type: Application
    Filed: August 24, 2005
    Publication date: April 17, 2008
    Inventors: Junichi Nagata, Yoshiyuki Asakawa
  • Patent number: 7288925
    Abstract: In a band gap reference voltage circuit, a band gap cell circuit composed of two transistors is driven with different current densities under a bias condition in which first and second reference voltages output in accordance with the operating states of the two transistors are equal to each other, thereby outputting a band gap reference voltage from a reference voltage output line. A differential amplifying circuit that is supplied with the first and second reference voltages as differential input signals subjects the differential input signals thus supplied to differential amplification. A level shift circuit is connected between a power supply line and the reference voltage output line and supplied with an output voltage of the differential amplifying circuit to carry out a level shift operation on the output voltage concerned.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: October 30, 2007
    Assignee: DENSO Corporation
    Inventor: Junichi Nagata
  • Publication number: 20070171590
    Abstract: An overcurrent detection circuit for detecting an overcurrent condition in an output transistor connected in series with an electrical load includes a pair of transistors having input terminals connected together. The pair of transistors is interposed between a current mirror circuit and a resistor and between the current mirror circuit and a detection transistor capable of being turned on at the same time as the output transistor. When a voltage is applied to the input terminals of the pair of the transistors, output terminals of the current mirror circuit are fixed at the same potential. Thus, even when an early effect occurs in the current mirror circuit, an electric current flowing through the resistor becomes equal to that flowing through the detection transistor. The overcurrent detection circuit can accurately detect the overcurrent condition based on a voltage drop across the resistor.
    Type: Application
    Filed: January 18, 2007
    Publication date: July 26, 2007
    Applicant: DENSO CORPORATION
    Inventors: Junichi Nagata, Masayuki Kominami
  • Patent number: 7167030
    Abstract: A drive circuit that supplies electric power to an electric load from a DC electric source includes a pair of series-connected first and second MOSFETS of the same conduction type, a pair of clamp circuits respectively connected between the drains and gates of the first and second MOSFETS, a series circuit of a first resistor and a switch, a first test terminal; a second test terminal connected to a joint of the first and second MOSFETS, a third test terminal for operating the switch, a fourth test terminal connected a joint of the first resistor and the switch; and a second resistor connected between the gate of the second MOSFET and the first test terminal. The switch and the first resistor are connected between the gate and the source of the first MOSFET to close when the drive circuit is normally operated and to open when it is given a high voltage test.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: January 23, 2007
    Assignee: Denso Corporation
    Inventors: Masahiro Kitagawa, Akio Kojima, Junichi Nagata
  • Publication number: 20060231868
    Abstract: A semiconductor device includes: a plurality of transistors connected in series between a ground potential and a predetermined potential; an input terminal provided by a gate terminal of the first step transistor; a plurality of resistors connected in series between the ground potential and the predetermined potential; and an output terminal provided by a predetermined potential side terminal of the Nth step transistor. A gate terminal of each transistor other than the first step transistor is sequentially connected between neighboring two resistors. One of the resistors defined as an Ith step resistor has a resistance, which is smaller than a resistance of a (I+1)th step resistor.
    Type: Application
    Filed: April 18, 2006
    Publication date: October 19, 2006
    Applicant: DENSO CORPORATION
    Inventors: Akira Yamada, Hiroaki Himi, Nozomu Akagi, Junichi Nagata
  • Publication number: 20060158164
    Abstract: A series-regulator type of power supply circuit is provided. In the circuit, the emitter and collector of a transistor are connected to power input/output terminals. A control circuit controls a base current of the transistor based on the output voltage detected at the power output terminal and a given target voltage. A resistor circuit connects the base and the collector of the transistor. A bypass circuit connects the emitter and the base of the transistor and passes a bypass current. The accepting circuit connected to the power output terminal accepts (absorbs) current from an output current. An amount of the acceptance current is equal to or larger than an amount of the bypass current and a product of the bypass current and a resistance value of the resistance circuit is equal to or more than a difference between a voltage at the power input terminal and the target voltage.
    Type: Application
    Filed: January 10, 2006
    Publication date: July 20, 2006
    Applicant: DENSO CORPORATION
    Inventors: Akio Kojima, Junichi Nagata
  • Patent number: 7071671
    Abstract: A constant voltage supplying circuit including an output transistor is connected to a power source line and an output terminal. A base-emitter voltage of the output transistor is detected by a voltage detecting circuit composed of a transistor. A current-outputting circuit for supplying a current determined based on the voltage detected by the voltage detector to a reference voltage supplying circuit is used in the constant voltage supplying circuit. The reference voltage is supplied to a base of the output transistor to cancel a base-emitter voltage of the output transistor and to equalize the output voltage to a voltage generated in a reference voltage generating element included in the reference voltage supplying circuit. In this manner, the output voltage is kept constant notwithstanding variation of output current.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: July 4, 2006
    Assignee: Denso Corporation
    Inventors: Masahiro Kitagawa, Akio Kojima, Junichi Nagata
  • Publication number: 20060071690
    Abstract: In a band gap reference voltage circuit, a band gap cell circuit composed of two transistors is driven with different current densities under a bias condition in which first and second reference voltages output in accordance with the operating states of the two transistors are equal to each other, thereby outputting a band gap reference voltage from a reference voltage output line. A differential amplifying circuit that is supplied with the first and second reference voltages as differential input signals subjects the differential input signals thus supplied to differential amplification. A level shift circuit is connected between a power supply line and the reference voltage output line and supplied with an output voltage of the differential amplifying circuit to carry out a level shift operation on the output voltage concerned.
    Type: Application
    Filed: October 4, 2005
    Publication date: April 6, 2006
    Applicant: DENSO CORPORATION
    Inventor: Junichi Nagata
  • Publication number: 20050212568
    Abstract: A drive circuit that supplies electric power to an electric load from a DC electric source includes a pair of series-connected first and second MOSFETS of the same conduction type, a pair of clamp circuits respectively connected between the drains and gates of the first and second MOSFETS, a series circuit of a first resistor and a switch, a first test terminal; a second test terminal connected to a joint of the first and second MOSFETS, a third test terminal for operating the switch, a fourth test terminal connected a joint of the first resistor and the switch; and a second resistor connected between the gate of the second MOSFET and the first test terminal. The switch and the first resistor are connected between the gate and the source of the first MOSFET to close when the drive circuit is normally operated and to open when it is given a high voltage test.
    Type: Application
    Filed: February 24, 2005
    Publication date: September 29, 2005
    Inventors: Masahiro Kitagawa, Akio Kojima, Junichi Nagata
  • Publication number: 20050140350
    Abstract: A constant voltage supplying circuit including an output transistor is connected to a power source line and an output terminal. A base-emitter voltage of the output transistor is detected by a voltage detecting circuit composed of a transistor. A current-outputting circuit for supplying a current determined based on the voltage detected by the voltage detector to a reference voltage supplying circuit is used in the constant voltage supplying circuit. The reference voltage is supplied to a base of the output transistor to cancel a base-emitter voltage of the output transistor and to equalize the output voltage to a voltage generated in a reference voltage generating element included in the reference voltage supplying circuit. In this manner, the output voltage is kept constant notwithstanding variation of output current.
    Type: Application
    Filed: October 28, 2004
    Publication date: June 30, 2005
    Inventors: Masahiro Kitagawa, Akio Kojima, Junichi Nagata
  • Patent number: 6850047
    Abstract: The power supply PS includes a voltage detecting circuit VD for detecting a voltage level Vs inputted from an external voltage source, a boot strap circuit BS, andET connected in parallel with BS, a smoothing circuit SM connected with the BS output terminal and a regulating IC connected with BS and FET. The regulating IC includes VD, a transistor Tr and condenser C. Both when a PS switch is turned on and when VD detects that Vs (which once descended) reaches an ascending reference, a high level driving signal generated by VD is changed into a low level signal, thereby turning off Tr connected with C. Thus, until Tr completes charging up C, a duty ratio of a pulse width modulation (PWM) signal dependent on the SM output is made gradually greater, thereby surely preventing a rush current by turning on and off the FET by the PWM signal.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: February 1, 2005
    Assignee: Denso Corporation
    Inventors: Toru Itabashi, Takanori Ishikawa, Junichi Nagata
  • Patent number: 6804096
    Abstract: A load driving circuit controls a feed of a power supply voltage of a power supply to a load. A power MOSFET is connected in series with the power supply and the load. A load driving state such as disconnection and short circuit of the load is detected by comparing a predetermined reference voltage and a voltage of the load and MOSFET node. For this, a pull-up resistor is connected between the power supply and the load. A diode is connected between source and gate of the MOSFET. A transistor circuit is connected between source and gate of the MOSFET to discharge a gate capacitance of the MOSFET. In a non-feed mode, a driving current is made to flow in a control electrode of the transistor circuit. The magnitude of the driving current is preferably enough to operate the transistor circuit and the voltage drop caused by the driving current is preferably smaller than a difference between the power supply voltage and the predetermined reference voltage.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: October 12, 2004
    Assignee: Denso Corporation
    Inventor: Junichi Nagata
  • Patent number: 6785106
    Abstract: An integrated circuit device includes an output terminal for connection with a terminal of an external load, and first and second power supply terminals for connection with a terminal of an external power supply. A switching element is connected between the output terminal and the first power supply terminal. The switching element, the external load, and the external power supply form a load current flow path. An impedance circuit is connected between the output terminal and the second power supply terminal. An abnormality detection circuit operates for monitoring a voltage at the output terminal, and detecting an abnormal condition on the basis of the monitored voltage. A drive control circuit operates for driving and controlling the switching element.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: August 31, 2004
    Assignee: Denso Corporation
    Inventor: Junichi Nagata
  • Publication number: 20040113599
    Abstract: A series-regulator type of power supply circuit is provided. In the circuit, the emitter and collector of a transistor are connected to power input/output terminals. A control circuit controls a base current of the transistor based on the output voltage detected at the power output terminal and a given target voltage. A resistor circuit connects the base and the collector of the transistor. A bypass circuit connects the emitter and the base of the transistor and passes a bypass current. The accepting circuit connected to the power output terminal accepts (absorbs) current from an output current. An amount of the acceptance current is equal to or larger than an amount of the bypass current and a product of the bypass current and a resistance value of the resistance circuit is equal to or more than a difference between a voltage at the power input terminal and the target voltage.
    Type: Application
    Filed: June 25, 2003
    Publication date: June 17, 2004
    Inventors: Akio Kojima, Junichi Nagata
  • Publication number: 20040085052
    Abstract: The power supply PS includes a voltage detecting circuit VD for detecting a voltage level Vs inputted from an external voltage source, a boot strap circuit BS, andET connected in parallel with BS, a smoothing circuit SM connected with the BS output terminal and a regulating IC connected with BS and FET. The regulating IC includes VD, a transistor Tr and condenser C. Both when a PS switch is turned on and when VD detects that Vs (which once descended) reaches an ascending reference, a high level driving signal generated by VD is changed into a low level signal, thereby turning off Tr connected with C. Thus, until Tr completes charging up C, a duty ratio of a pulse width modulation (PWM) signal dependent on the SM output is made gradually greater, thereby surely preventing a rush current by turning on and off the FET by the PWM signal.
    Type: Application
    Filed: October 28, 2003
    Publication date: May 6, 2004
    Inventors: Toru Itabashi, Takanori Ishikawa, Junichi Nagata
  • Patent number: 6531855
    Abstract: A series circuit including a capacitor and a resistor for detecting variation of the output voltage of dc power supply is further provided. During startup, a charge current corresponding to the rising rate of the output voltage flows through the series circuit. This reduces the base current of the power transistor to suppress the rising rate to suppress overshoot and undershoot. A clamp circuit is provided to the differential amplifier for detecting the error voltage. This prevents the saturation in the differential amplifier or limit the voltage variation amplitude to accelerate the operation of the operational amplifier and suppress undershoot. A delay circuit for disabling to driving circuit for the power transistor for the initial interval may be further provided to suppress the initial rapid rise of the output voltage.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: March 11, 2003
    Assignee: Denso Corporation
    Inventors: Takeshi Miki, Junichi Nagata, Hiroyuki Ban
  • Patent number: 6518803
    Abstract: The present invention discloses an output circuit, by which it is possible to reduce power consumption while maintaining maximum voltage value to be outputted at high level. In this output circuit, a charge-and-discharge circuit uses a terminal voltage Vc of a capacitor as a trapezoidal wave voltage, and a drive circuit drives an output transistor based on the terminal voltage Vc, and a voltage Vo equal to the terminal voltage Vc is outputted to the load. A voltage detection circuit detects an emitter voltage (Vc+VF) of the transistor and generates an electric current proportional to the terminal voltage Vc. This electric current is turned to a base current of the output transistor via a variable current circuit. Therefore, a base current proportional to the output voltage Vo is supplied to the output transistor.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: February 11, 2003
    Assignee: Denso Corporation
    Inventors: Junichi Nagata, Akio Kojima
  • Publication number: 20030021073
    Abstract: A load driving circuit controls a feed of a power supply voltage of a power supply to a load. A power MOSFET is connected in series with the power supply and the load. A load driving state such as disconnection and short circuit of the load is detected by comparing a predetermined reference voltage and a voltage of the load and MOSFET node. For this, a pull-up resistor is connected between the power supply and the load. A diode is connected between source and gate of the MOSFET. A transistor circuit is connected between source and gate of the MOSFET to discharge a gate capacitance of the MOSFET. In a non-feed mode, a driving current is made to flow in a control electrode of the transistor circuit. The magnitude of the driving current is preferably enough to operate the transistor circuit and the voltage drop caused by the driving current is preferably smaller than a difference between the power supply voltage and the predetermined reference voltage.
    Type: Application
    Filed: July 29, 2002
    Publication date: January 30, 2003
    Inventor: Junichi Nagata
  • Patent number: 6475266
    Abstract: An exhaust gas recovery method and apparatus including: a first process in which volatile organic compound gas in exhaust gas from a exhaust gas discharging source is absorbed into water by a scrubber; a second process in which water including the volatile organic compound, which is obtained in the first process, is frozen and the volatile organic compound herein concentrated such that the water including the volatile organic compound is separated into water including a high concentration of the volatile organic compound, level of concentration being higher than that of the water including the volatile organic compound which is obtained in the first process, and ice; a third process in which cold of the ice obtained in the second process is used; and a fourth process in which the water including a high concentration of the volatile organic compound, which is obtained in the second process, is reused, is provided.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: November 5, 2002
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Kenji Hayashi, Junichi Nagata, Shinichi Funabashi
  • Patent number: 6465996
    Abstract: A constant voltage circuit robust to the input voltage lowering is disclosed. The invention is applied to a constant voltage circuit fed with an input voltage through first and second power conductors for transferring the input voltage to a load as an output voltage through an output transistor. An inventive constant voltage circuit is provided with a substitute circuit, responsive to a detection of the lowing of the input voltage to a predetermined voltage, for providing a substitute output path that is connected in parallel with the output transistor. Doing this minimize the degree of lowering of the second voltage due to the lowering of said first voltage. The output transistor may be nay of NPN and PNP transistors and P-type and N-type MOS FETs.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: October 15, 2002
    Assignee: Denso Corporation
    Inventors: Junichi Nagata, Kiyoshi Yamamoto, Hirokazu Itakura, Masahiro Kitagawa, Hiroyuki Ban, Hiroyuki Kawabata, Shinichi Maeda