Patents by Inventor Junichi Okamura

Junichi Okamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9956633
    Abstract: A wave soldering tank includes a soldering tank body for housing molten solder and a solder feed chamber disposed within the soldering tank body. An axial-flow, multiple-blade screw-type pump is disposed so as to draw molten solder into the solder feed chamber through an inlet and discharge the molten solder through an outlet. In a preferred embodiment, the pump includes a rotatable hub and a plurality of helical blades secured to the hub at equal intervals in the circumferential direction of the hub, each of the blades overlapping an adjoining one of the blades when the blades are viewed in the axial direction of the impeller.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: May 1, 2018
    Assignee: SENJU METAL INDUSTRY CO., LTD.
    Inventors: Akira Takaguchi, Issaku Sato, Noboru Hashimoto, Junichi Okamura
  • Patent number: 9681231
    Abstract: A digital/analog conversion apparatus to convert a digital signal into an analog signal. The digital/analog conversion apparatus can generate a high-quality analog signal, even when elements configuring the digital/analog conversion apparatus have variance, with high resolution and a small circuit size. The data conversion apparatus is provided with a first data converter to reduce the number of bits of an input signal, a second data converter to convert the format of the first output signal, and a third data converter for conversion into a code which corresponds to the history of the output from the second data converter.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: June 13, 2017
    Assignee: TRIGENCE SEMICONDUCTOR, INC.
    Inventors: Akira Yasuda, Junichi Okamura
  • Publication number: 20160205471
    Abstract: A digital/analog conversion apparatus to convert a digital signal into an analog signal. The digital/analog conversion apparatus can generate a high-quality analog signal, even when elements configuring the digital/analog conversion apparatus have variance, with high resolution and a small circuit size. The data conversion apparatus is provided with a first data converter to reduce the number of bits of an input signal, a second data converter to convert the format of the first output signal, and a third data converter for conversion into a code which corresponds to the history of the output from the second data converter.
    Type: Application
    Filed: January 12, 2016
    Publication date: July 14, 2016
    Inventors: Akira Yasuda, Junichi Okamura
  • Patent number: 9276540
    Abstract: A digital/analog conversion apparatus to convert a digital signal into an analog signal. The digital/analog conversion apparatus can generate a high-quality analog signal, even when elements configuring the digital/analog conversion apparatus have variance, with high resolution and a small circuit size. The data conversion apparatus is provided with a first data converter to reduce the number of bits of an input signal, a second data converter to convert the format of the first output signal, and a third data converter for conversion into a code which corresponds to the history of the output from the second data converter.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: March 1, 2016
    Assignee: TRIGENCE SEMICONDUCTORS, INC.
    Inventors: Akira Yasuda, Junichi Okamura
  • Patent number: 8423165
    Abstract: A digital/analog conversion apparatus for converting a digital signal into an analog signal. The digital/analog conversion apparatus can generate a high-quality analog signal, even when elements configuring the digital/analog conversion apparatus have variance, with high resolution and a small circuit size. The data conversion apparatus is provided with a first data converter for reducing the number of bits of an input signal, a second data converter for converting the format of the first output signal, and a third data converter for conversion into a code which corresponds to the history of the output from the second data converter.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: April 16, 2013
    Assignee: Trigence Semiconductor, Inc.
    Inventors: Akira Yasuda, Junichi Okamura
  • Publication number: 20120255987
    Abstract: A wave soldering tank includes a soldering tank body for housing molten solder and a solder feed chamber disposed within the soldering tank body. An axial-flow, multiple-blade screw-type pump is disposed so as to draw molten solder into the solder feed chamber through an inlet and discharge the molten solder through an outlet. In a preferred embodiment, the pump includes a rotatable hub and a plurality of helical blades secured to the hub at equal intervals in the circumferential direction of the hub, each of the blades overlapping an adjoining one of the blades when the blades are viewed in the axial direction of the impeller.
    Type: Application
    Filed: June 19, 2012
    Publication date: October 11, 2012
    Inventors: Akira Takaguchi, Issaku Sato, Noboru Hashimoto, Junichi Okamura
  • Patent number: 8215534
    Abstract: A wave soldering tank includes a soldering tank body for housing molten solder and a solder feed chamber disposed within the soldering tank body. An axial-flow, multiple-blade screw-type pump is disposed so as to draw molten solder into the solder feed chamber through an inlet and discharge the molten solder through an outlet. In a preferred embodiment, the pump includes a rotatable hub and a plurality of helical blades secured to the hub at equal intervals in the circumferential direction of the hub, each of the blades overlapping an adjoining one of the blades when the blades are viewed in the axial direction of the impeller.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: July 10, 2012
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Akira Takaguchi, Issaku Sato, Noboru Hashimoto, Junichi Okamura
  • Patent number: 7584434
    Abstract: A map database site S comprises a map information database Sb for accumulating the map data constructed of units for displaying of unit images m each having a display range smaller than a display range of a map image M corresponding to one page of a map image displayed on a user terminal T, in association with position data indicating the display ranges of the individual unit images m. A user terminal T comprises map-image display means for combining the map data of a plurality of units with each other on the basis of the associated position data, which are read out from the map information database Sb provided in the map database site S and transmitted from the map database site S, to form the one-page map image M for display.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: September 1, 2009
    Assignees: Pioneer Corporation, Increment P Corporation
    Inventor: Junichi Okamura
  • Publication number: 20090110217
    Abstract: A digital/analog conversion apparatus for converting a digital signal into an analog signal. The digital/analog conversion apparatus can generate a high-quality analog signal, even when elements configuring the digital/analog conversion apparatus have variance, with high resolution and a small circuit size. The data conversion apparatus is provided with a first data converter for reducing the number of bits of an input signal, a second data converter for converting the format of the first output signal, and a third data converter for conversion into a code which corresponds to the history of the output from the second data converter.
    Type: Application
    Filed: October 1, 2008
    Publication date: April 30, 2009
    Applicant: Trigence Semiconductor, Inc.
    Inventors: Akira Yasuda, Junichi Okamura
  • Publication number: 20080093417
    Abstract: A wave soldering tank includes a soldering tank body for housing molten solder and a solder feed chamber disposed within the soldering tank body. An axial-flow, multiple-blade screw-type pump is disposed so as to draw molten solder into the solder feed chamber through an inlet and discharge the molten solder through an outlet. In a preferred embodiment, the pump includes a rotatable hub and a plurality of helical blades secured to the hub at equal intervals in the circumferential direction of the hub, each of the blades overlapping an adjoining one of the blades when the blades are viewed in the axial direction of the impeller.
    Type: Application
    Filed: October 8, 2004
    Publication date: April 24, 2008
    Inventors: Akira Takaguchi, Issaku Sato, Noboru Hashimoto, Junichi Okamura
  • Patent number: 7158441
    Abstract: A semiconductor integrated circuit in which multiphase clock signals having the same phase difference are supplied from a multi-stage differential ring oscillator to other circuits, the multiphase clock signals can be prevented from being degraded in waveform due to electrostatic coupling between wirings of the multiphase clock signals and also wired in as small an area as possible. The semiconductor integrated circuit includes: multiple stages of amplifier circuits, connected in a ring form, for performing oscillating operation; a logic circuit for performing logic operation on the basis of predetermined ones of output signals of the multiple stages of amplifier circuits to output a plurality of clock signals having different phases from each other and duties not equal to 0.5; and a plurality of wirings for transmitting the plurality of clock signals output from the logic circuit.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: January 2, 2007
    Assignee: Thine Electronics, Inc.
    Inventor: Junichi Okamura
  • Patent number: 7129795
    Abstract: A semiconductor integrated circuit in which, when leading out multiple-phase clock signal wirings from the ring oscillator circuit capable of oscillating at a high frequency, increase in the area of the substrate and deterioration in the clock phase accuracy caused by the non-uniform stray capacitances among the multiple-phase clock signal wirings are prevented. The semiconductor integrated circuit includes: N-stage amplifying circuits connected in a form of a ring to perform oscillating operation, which amplifying circuits are arranged in a semiconductor substrate to be divided into a plurality of rows, wherein in each row an amplifying circuit of “m?1”th stage and an amplifying circuit of “m”th stage are not adjacent to each other, where m is an arbitrary integer number within a range from 2 to N; and a plurality of wirings for respectively leading out a plurality of output signals from the amplifying circuits disposed in one of the plurality of rows.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: October 31, 2006
    Assignee: Thine Electronics, Inc.
    Inventor: Junichi Okamura
  • Patent number: 7043202
    Abstract: A phase-selective type frequency modulator capable of easing the restriction on a phase range of a modulated clock signal. The phase-selective type frequency modulator includes a multiphase clock signal generating circuit 101 for generating N-phase clock signals; a control circuit 104 for sequentially activating one of first group of clock selection signals indicating a clock signal to be selected from the N-phase clock signals; an edge appearance time adjustment circuit 103 for adjusting a rising edge appearance time and/or a trailing edge appearance time of the first group of clock selection signals outputted from the control circuit 104 to output second group of clock selection signals; and a modulated clock signal generating circuit 102 for selecting one clock signal from the N-phase clock signals in accordance with an activated state of the second group of clock selection signals outputted from the edge appearance time adjustment circuit 103 to output a modulated clock signal MCK.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: May 9, 2006
    Assignee: Thine Electronics, Inc.
    Inventors: Seiichi Ozawa, Junichi Okamura
  • Publication number: 20060025094
    Abstract: A phase-selective type frequency modulator capable of easing the restriction on a phase range of a modulated clock signal. The phase-selective type frequency modulator includes a multiphase clock signal generating circuit 101 for generating N-phase clock signals; a control circuit 104 for sequentially activating one of first group of clock selection signals indicating a clock signal to be selected from the N-phase clock signals; an edge appearance time adjustment circuit 103 for adjusting a rising edge appearance time and/or a trailing edge appearance time of the first group of clock selection signals outputted from the control circuit 104 to output second group of clock selection signals; and a modulated clock signal generating circuit 102 for selecting one clock signal from the N-phase clock signals in accordance with an activated state of the second group of clock selection signals outputted from the edge appearance time adjustment circuit 103 to output a modulated clock signal MCK.
    Type: Application
    Filed: December 8, 2003
    Publication date: February 2, 2006
    Inventors: Seiichi Ozawa, Junichi Okamura
  • Patent number: 6911850
    Abstract: In a semiconductor integrated circuit including a phase comparison circuit for a DLL in a reception circuit for receiving serial digital transmission signals, phase detection characteristics of the phase comparison circuit are improved while preventing false lock so as to improve response speed and locking accuracy of the DLL as a whole.
    Type: Grant
    Filed: May 14, 2002
    Date of Patent: June 28, 2005
    Assignee: Thine Electronics, Inc.
    Inventor: Junichi Okamura
  • Publication number: 20050104673
    Abstract: A semiconductor integrated circuit in which multiphase clock signals having the same phase difference are supplied from a multi-stage differential ring oscillator to other circuits, the multiphase clock signals can be prevented from being degraded in waveform due to electrostatic coupling between wirings of the multiphase clock signals and also wired in as small an area as possible. The semiconductor integrated circuit includes: multiple stages of amplifier circuits, connected in a ring form, for performing oscillating operation; a logic circuit for performing logic operation on the basis of predetermined ones of output signals of the multiple stages of amplifier circuits to output a plurality of clock signals having different phases from each other and duties not equal to 0.5; and a plurality of wirings for transmitting the plurality of clock signals output from the logic circuit.
    Type: Application
    Filed: December 13, 2004
    Publication date: May 19, 2005
    Inventor: Junichi Okamura
  • Patent number: 6864734
    Abstract: A semiconductor integrated circuit which realizes a reception circuit that can stably detect symbol values even in a case where, in the reception of serial transmission data, the serial transmission data has its phase shifted relative to the sampling clock signals or has its waveform degraded due to the deviation of the delay of a signal in a transmission line.
    Type: Grant
    Filed: December 25, 2001
    Date of Patent: March 8, 2005
    Assignee: Thine Electronics, lnc.
    Inventor: Junichi Okamura
  • Publication number: 20040212442
    Abstract: A semiconductor integrated circuit in which, when leading out multiple-phase clock signal wirings from the ring oscillator circuit capable of oscillating at a high frequency, increase in the area of the substrate and deterioration in the clock phase accuracy caused by the non-uniform stray capacitances among the multiple-phase clock signal wirings are prevented. The semiconductor integrated circuit includes: N-stage amplifying circuits connected in a form of a ring to perform oscillating operation, which amplifying circuits are arranged in a semiconductor substrate to be divided into a plurality of rows, wherein in each row an amplifying circuit of “m−1”th stage and an amplifying circuit of “m”th stage are not adjacent to each other, where m is an arbitrary integer number within a range from 2 to N; and a plurality of wirings for respectively leading out a plurality of output signals from the amplifying circuits disposed in one of the plurality of rows.
    Type: Application
    Filed: March 5, 2004
    Publication date: October 28, 2004
    Inventor: Junichi Okamura
  • Publication number: 20040090828
    Abstract: A semiconductor integrated circuit in which multiphase clock signals having the same phase difference are supplied from a multi-stage differential ring oscillator to other circuits, the multiphase clock signals can be prevented from being degraded in waveform due to electrostatic coupling between wirings of the multiphase clock signals and also wired in as small an area as possible. The semiconductor integrated circuit includes: multiple stages of amplifier circuits, connected in a ring form, for performing oscillating operation; a logic circuit for performing logic operation on the basis of predetermined ones of output signals of the multiple stages of amplifier circuits to output a plurality of clock signals having different phases from each other and duties not equal to 0.5; and a plurality of wirings for transmitting the plurality of clock signals output from the logic circuit.
    Type: Application
    Filed: January 15, 2003
    Publication date: May 13, 2004
    Inventor: Junichi Okamura
  • Publication number: 20040051571
    Abstract: A semiconductor integrated circuit which realizes a reception circuit that can stably detect symbol values even in a case where, in the reception of serial transmission data, the serial transmission data has its phase shifted relative to the sampling clock signals or has its waveform degraded due to the deviation of the delay of a signal in a transmission line.
    Type: Application
    Filed: August 11, 2003
    Publication date: March 18, 2004
    Inventor: Junichi Okamura