Abstract: An input protection circuit is formed on a semiconductor substrate. A resistive element of an impurity diffusion region is electrically isolated from a main region of the substrate by a first double well structure. A bipolar transistor is connected to the resistive element which is electrically isolated from the main region of the substrate by a second double well structure. An input pad is connected to the bipolar transistor.

Abstract: A dynamic random access memory includes a dynamic memory cell having a transfer N-channel MOS transistor and a capacitive element for storing data which is connected to the transfer N-channel MOS transistor, a word line connected to a gate of the transfer N-channel transistor, of the dynamic memory cell, and a word line driving voltage source, to which power voltage is input for raising the input power voltage to generate a word line driving voltage.

Abstract: An integrated circuit pattern of a sense amplifier is disclosed. The sense amplifier includes a sense circuit connected to a memory array and a column gate. The sense circuit includes N-MOSFETs cross-coupled between paired bit lines. The column gate includes an N-MOSFET for connecting the bit line to a data line and an N-MOSFET for connecting the other bit line to another data line. The N-MOSFET contained in the sense circuit and the N-MOSFET contained in the column gate are integrated in one element region. Further, the N-MOSFET contained in the sense circuit and the N-MOSFET contained in the column gate are integrated in another element region.

Abstract: In a DRAM or similar memory having sense amplifiers coupled to memory cells, a sense amplifier is switchably connected to a discharge circuit to discharge the terminal of the sense amplifier at high speed. The node of the sense amplifier is also coupled to a discharge circuit which discharges the node at a slower speed. In operation, only the node of a selected sense amplifier is discharged at high speed, while other non-selected sense amplifiers are activated by discharging the sense amplifier node at a lower speed. This mode of operation allows for the high speed activation of the selected sense amplifier with the associated current consumption being limited to that necessary to discharge the individual sense amplifier selected. The two discharge circuits may be two N channel MOS transistors connecting the node of the sense amplifier to two drive lines driven by independent circuits.

Abstract: A semiconductor memory comprising core blocks 1, 2, 3 and 4 each comprising memory cell arrays each having a plurality of memory cells in a matrix and sense amplifiers and decoders accompanying the memory cell arrays. An inter-block region is arranged among the core blocks wherein data signal lines, address signal lines and control signal lines are provided. Pad arrays IO Pad and A Pad each comprising a plurality of pads and buses IO Bus and A Bus are arranged among the core blocks. The buses A Bus are jogged in a connection region. The buses IO Bus and A Bus are arranged successively in the inter-block region and the data signal lines, the address signal lines and the control signal lines are connected to the buses A Bus and IO Bus in the inter-block region.

Abstract: An integrated circuit pattern of a sense amplifier is disclosed. The sense amplifier includes a sense circuit connected to a memory array and a column gate. The sense circuit includes N-MOSFETs cross-coupled between paired bit lines. The column gate includes an N-MOSFET for connecting the bit line to a data line and an N-MOSFET for connecting the other bit line to another data line. The N-MOSFET contained in the sense circuit and the N-MOSFET contained in the column gate are integrated in one element region. Further, the N-MOSFET contained in the sense circuit and the N-MOSFET contained in the column gate are integrated in another element region.

Abstract: A dynamic random access memory according to the present invention comprises a plurality of dynamic memory cells arranged in rows and columns, a word line connected to the memory cells on the same row, a bit line connected to the memory cells on the same column, a word line selecting circuit having a word line selecting function of selecting an arbitrary one of the rows in response to an internal address signal, a word line driving voltage source, a word line driving circuit having at least one driving MOS transistor connected between the word line driving voltage source and the word line, for driving the word line in response to an output signal of the word line selecting circuit, and a control circuit for, in response to a voltage stress test control signal input from outside, controlling the word line driving circuit so that the word line driving circuit drives word lines more than those selected in a normal operation mode upon receiving an external address signal.