Patents by Inventor Junichi Okamura
Junichi Okamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040036087Abstract: In a semiconductor integrated circuit including a phase comparison circuit for a DLL in a reception circuit for receiving serial digital transmission signals, phase detection characteristics of the phase comparison circuit are improved while preventing false lock so as to improve response speed and locking accuracy of the DLL as a whole.Type: ApplicationFiled: January 2, 2003Publication date: February 26, 2004Inventor: Junichi Okamura
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Patent number: 6532167Abstract: A voltage generator for outputting an output voltage at an output terminal thereof includes a driver MOS transistor of a first conductivity type having a first end connected to said output terminal and a capacitor connected between the output terminal and a second voltage node. The capacitor comprises a plurality of trench capacitors formed in a semiconductor substrate.Type: GrantFiled: July 13, 2001Date of Patent: March 11, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Kaneko, Junichi Okamura
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Publication number: 20030038845Abstract: A map database site S comprises a map information database Sb for accumulating the map data constructed of units for displaying of unit images m each having a display range smaller than a display range of a map image M corresponding to one page of a map image displayed on a user terminal T, in association with position data indicating the display ranges of the individual unit images m. A user terminal T comprises map-image display means for combining the map data of a plurality of units with each other on the basis of the associated position data, which are read out from the map information database Sb provided in the map database site S and transmitted from the map database site S, to form the one-page map image M for display.Type: ApplicationFiled: July 23, 2002Publication date: February 27, 2003Applicant: Pioneer CorporationInventor: Junichi Okamura
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Publication number: 20030033202Abstract: A system 1 and method for producing and managing an advertisement is disclosed having an advertisement client head terminal 2 of an advertisement client who orders an object advertisement to be produced, an area base terminal 3 at each of area bases of the advertisement client, a production company terminal 4 of a production company which produces an advertisement part and advertisement design information, an advertisement production management server 5 which executes preliminary processing of separate examination for the advertisement part and the advertisement design information to produce a complete package to enable the advertisement to be altered upon receipt of an audience response, a broadcast entrepreneur 6 who executes separate examination of the advertisement and provides a broadcast of the advertisement, an audience terminal 7 from which the advertisement is viewed, and a response server 8 which collects the audience response.Type: ApplicationFiled: August 9, 2002Publication date: February 13, 2003Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yukio Ogawa, Motomu Ootawa, Takashi Yamashita, Shigeo Nomura, Junichi Okamura, Keishi Higashi, Yukiteru Nozawa
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Patent number: 6477079Abstract: A voltage generator for outputting an output voltage at an output terminal thereof includes a driver MOS transistor of a first conductivity type having a first end connected to said output terminal and a capacitor connected between the output terminal and a second voltage node. The capacitor comprises a plurality of trench capacitors formed in a semiconductor substrate.Type: GrantFiled: May 18, 1999Date of Patent: November 5, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Kaneko, Junichi Okamura
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Publication number: 20020110017Abstract: A voltage generator for outputting an output voltage at an output terminal thereof includes a driver MOS transistor of a first conductivity type having a first end connected to said output terminal and a capacitor connected between the output terminal and a second voltage node. The capacitor comprises a plurality of trench capacitors formed in a semiconductor substrate.Type: ApplicationFiled: July 13, 2001Publication date: August 15, 2002Inventors: Tetsuya Kaneko, Junichi Okamura
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Publication number: 20020101426Abstract: A map data memory area for storing map data read from external is set in a hard disk of an information terminal, the map information read from external is stored in the map data memory area, if the information terminal is requested to display a map image, whether or not the map data requested to be displayed is stored in the map data memory area is retrieved, if the map data requested to be displayed is stored in the map data memory area, the map data stored in the map data memory area is read and is displayed on the information terminal, and if the map data requested to be displayed is not stored in the map data memory area, the map data to be displayed is read from external and is displayed on the information terminal, and the read map data is stored in the map data memory area.Type: ApplicationFiled: January 31, 2002Publication date: August 1, 2002Applicant: PIONEER CORPORATIONInventor: Junichi Okamura
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Patent number: 6381186Abstract: A dynamic random access memory includes a plurality of dynamic memory cells arranged in rows and columns, a word line connected to the memory cells on the same row, a bit line connected to the memory cells on the same column, a word line selecting circuit having a word line selecting function of selecting an arbitrary one of the rows in response to an internal address signal, a word line driving voltage source, a word line driving circuit having at least one driving MOS transistor connected between the word line driving voltage source and the word line, for driving the word line in response to an output signal of the word line selecting circuit, and a control circuit for, in response to a voltage stress test control signal input from outside, controlling the word line driving circuit so that the word line driving circuit drives word lines more than those selected in a normal operation mode upon receiving an external address signal.Type: GrantFiled: August 28, 2001Date of Patent: April 30, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Junichi Okamura, Tohru Furuyama
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Publication number: 20020048205Abstract: A dynamic random access memory according to the present invention comprises a plurality of dynamic memory cells arranged in rows and columns, a word line connected to the memory cells on the same row, a bit line connected to the memory cells on the same column, a word line selecting circuit having a word line selecting function of selecting an arbitrary one of the rows in response to an internal address signal, a word line driving voltage source, a word line driving circuit having at least one driving MOS transistor connected between the word line driving voltage source and the word line, for driving the word line in response to an output signal of the word line selecting circuit, and a control circuit for, in response to a voltage stress test control signal input from outside, controlling the word line driving circuit so that the word line driving circuit drives word lines more than those selected in a normal operation mode upon receiving an external address signal.Type: ApplicationFiled: August 28, 2001Publication date: April 25, 2002Applicant: Kabushiki Kaisha ToshibaInventors: Junichi Okamura, Tohru Furuyama
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Patent number: 6317366Abstract: A semiconductor memory device includes a memory cell having a transfer N-channel MOS transistor and a capacitive element for storing data which is connected to the transfer N-channel MOS transistor, a word line connected to a gate of the transfer N-channel transistor, of the memory cell, a charge pump circuit generating an internal power supply voltage which is boosted up from a power supply voltage, and outputting the internal power supply voltage, and a decoder circuit which receives address signals and has a P-channel MOS transistor for receiving the internal power supply voltage, the decoder circuit generating a word line selecting signal.Type: GrantFiled: August 1, 2000Date of Patent: November 13, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Junichi Okamura, Tohru Furuyama
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Patent number: 6307796Abstract: A dynamic random access memory includes a plurality of dynamic memory cells arranged in rows and columns, a word line connected to the memory cells on the same row, a bit line connected to the memory cells on the same column, a word line selecting circuit having a word line selecting function of selecting an arbitrary one of the rows in response to an internal address signal, a word line driving voltage source, a word line driving circuit having at least one driving MOS transistor connected between the word line driving voltage source and the word line, for driving the word line in response to an output signal of the word line selecting circuit, and a control circuit for, in response to a voltage stress test control signal input from outside, controlling the word line driving circuit so that the word line driving circuit drives word lines more than those selected in a normal operation mode upon receiving an external address signal.Type: GrantFiled: October 16, 2000Date of Patent: October 23, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Junichi Okamura, Tohru Furuyama
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Publication number: 20010021138Abstract: A voltage generator for outputting an output voltage at an output terminal thereof includes a driver MOS transistor of a first conductivity type having a first end connected to said output terminal and a capacitor connected between the output terminal and a second voltage node. The capacitor comprises a plurality of trench capacitors formed in a semiconductor substrate.Type: ApplicationFiled: May 18, 1999Publication date: September 13, 2001Inventors: TETSUYA KANEKO, JUNICHI OKAMURA
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Patent number: 6181618Abstract: The present invention is to provide a semiconductor memory device capable of realizing a high speed sensing operation and an enlarged sense margin, for ensuring the sensing operation even with a low power source voltage by connecting the bit line of the memory cell array portion and the bit line of the sense amplifier portion via the P-type transfer gate, having the bit line amplitude of the sense amplifier potion larger than the bit line amplitude of the memory cell array portion, and having different precharge voltages for the bit line of the sense amplifier portion and the bit line of the memory cell array portion.Type: GrantFiled: March 10, 1998Date of Patent: January 30, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Inaba, Kenji Tsuchida, Junichi Okamura
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Patent number: 6166975Abstract: A dynamic random access memory includes a dynamic memory cell having a transfer N-channel MOS transistor and a capacitive element for storing data which is connected to the transfer N-channel MOS transistor, a word line connected to a gate of the transfer N-channel transistor, of the dynamic memory cell, and a word line driving voltage source, to which power voltage is input for raising the input power voltage to generate a word line driving voltage.Type: GrantFiled: December 21, 1999Date of Patent: December 26, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Junichi Okamura, Tohru Furuyama
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Patent number: 6140805Abstract: A voltage generator for generating an output voltage at an output terminal thereof which includes a first transistor of a first channel conductivity type having a first end connected to the output terminal and a feedback regulator connected to the output terminal. A switch is connected between a voltage node and a second end of the first transistor, the switch receiving a switching signal.Type: GrantFiled: May 18, 1999Date of Patent: October 31, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Kaneko, Junichi Okamura
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Patent number: 6101148Abstract: A dynamic random access memory includes a dynamic memory cell having a transfer N-channel MOS transistor and a capacitive element for storing data which is connected to the transfer N-channel MOS transistor, a word line connected to a gate of the transfer N-channel transistor, of the dynamic memory cell, and a word line driving voltage source, to which power voltage is input for raising the input power voltage to generate a word line driving voltage.Type: GrantFiled: August 6, 1997Date of Patent: August 8, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Junichi Okamura, Tohru Furuyama
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Patent number: 5929492Abstract: An integrated circuit pattern of a sense amplifier is disclosed. The sense amplifier includes a sense circuit connected to a memory array and a column gate. The sense circuit includes N-MOSFETs cross-coupled between paired bit lines. The column gate includes an N-MOSFET for connecting the bit line to a data line and an N-MOSFET for connecting the other bit line to another data line. The N-MOSFET contained in the sense circuit and the N-MOSFET contained in the column gate are integrated in one element region. Further, the N-MOSFET contained in the sense circuit and the N-MOSFET contained in the column gate are integrated in another element region.Type: GrantFiled: June 5, 1997Date of Patent: July 27, 1999Assignee: Kabushiki Kaisha ToshibaInventor: Junichi Okamura
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Patent number: 5894442Abstract: The present invention relates to a semiconductor memory device which, while preventing an operation error, achieves the shortening of a precharging time and, hence, further shortening of a cycle time of a memory operation. The equalizing control circuit includes a latch circuit. An equalizing control circuit receives a signal WLact and a signal X-ADR from a predecoder and outputs an equalizing signal EQS from these two signals. A latch circuit in the equalizing control circuit is set (the inactivation of an equalizing signal) by a signal X-ADR which is activated with an internal RAS signal and holds its state. The latch circuit is reset (the activation of the equalizing signal) by a signal corresponding to a word line active signal WLact with a word line inactivated. By doing so, it is possible to provide the equalizing control circuit not directly depending upon the internal RAS signal.Type: GrantFiled: February 26, 1997Date of Patent: April 13, 1999Assignee: Kabushiki Kaisha ToshibaInventor: Junichi Okamura
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Patent number: 5812478Abstract: A semiconductor memory including first, second, and third data busses, and first and second memory cell arrays arranged among the first, second, and third data busses. During operation of the semiconductor memory, a first, a second, and a third circuit selectively couple the first, second, and third data busses to a fourth and a fifth data bus. Additionally, there is provided first and second buffer circuits, which are respectively coupled to the fourth and the fifth data busses, and a sixth data bus, which is commonly coupled to the first and second buffer circuits. A control circuit is used to control the operation of the switch circuits. In preferred embodiments, the number of buffer circuits in the semiconductor memory is less than or equal to the number of memory cell arrays.Type: GrantFiled: May 22, 1996Date of Patent: September 22, 1998Assignee: Kabushiki Kaisha ToshibaInventor: Junichi Okamura
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Patent number: 5740120Abstract: A semiconductor memory including first, second, and third data busses, and first and second memory cell arrays arranged among the first, second, and third data busses. During operation of the semiconductor memory, a first, a second, and a third switch circuit selectively couple the first, second, and third data busses to a fourth and a fifth data bus. Additionally, there is provided first and second buffer circuits, which are respectively coupled to the fourth and the fifth data busses, and a sixth data bus, which is commonly coupled to the first and second buffer circuits. A control circuit is used to control the operation of the switch circuits. In a preferred embodiment, the semiconductor memory has an equal number of buffer circuits and memory cell arrays.Type: GrantFiled: January 4, 1996Date of Patent: April 14, 1998Assignee: Kabushiki Kaisha ToshibaInventor: Junichi Okamura