Abstract: One code (a compressed redundant code) is created based on a plurality of first redundant codes, each created on the basis of a plurality of data units, and this compressed redundant code is written to a nonvolatile storage area. This compressed redundant code is used to restore either a data element constituting a multiple-failure data, or a first redundant code corresponding to the multiple-failure data, which is stored in an unreadable sub-storage area of a partially failed storage device, and to restore the data element constituting the multiple-failure data which is stored in a sub-storage area of a completely failed storage device, based on the restored either data element or first redundant code, and either another data element constituting the multiple-failure data or the first redundant code corresponding to the multiple-failure data.

Abstract: The present invention enables to update a program in a storage control device while processing access requests, without imposing any burden on a host. When execution of updating of a program is commanded from a management terminal, an update control unit starts within the controller which is the object of updating. After a host I/F unit has been connected to an access request processing unit within another controller by a connection control unit, the update control unit updates a program which is stored in a program memory or a boot disk. When this updating is completed, the update control unit reconnects the host I/F unit to its access processing unit by the connection control unit. Since the stored contents of data memories are synchronized, the other access request processing unit can continue processing access requests from the host in place one access request processing unit.

Abstract: A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

Abstract: A storage group configured by a plurality of storage devices is configured by a plurality of storage sub-groups, and the respective storage sub-groups are configured from two or more storage devices. A sub-group storage area, which is the storage area of the respective storage sub-groups, is configured by a plurality of rows of sub-storage areas. A data set, which is configured by a plurality of data elements configuring a data unit, and a second redundancy code created on the basis of this data unit, is written to a row of sub-storage areas, a compressed redundancy code is created on the basis of two or more first redundancy codes respectively created based on two or more data units of two or more storage sub-groups, and this compressed redundancy code is written to a nonvolatile storage area that differs from the above-mentioned two or more storage sub-groups.

Abstract: One code (a compressed redundant code) is created based on a plurality of first redundant codes, each created on the basis of a plurality of data units, and this compressed redundant code is written to a nonvolatile storage area. This compressed redundant code is used to restore either a data element constituting a multiple-failure data, or a first redundant code corresponding to the multiple-failure data, which is stored in an unreadable sub-storage area of a partially failed storage device, and to restore the data element constituting the multiple-failure data which is stored in a sub-storage area of a completely failed storage device, based on the restored either data element or first redundant code, and either another data element constituting the multiple-failure data or the first redundant code corresponding to the multiple-failure data.

Abstract: A plurality of CPU cores each have control rights for logical storage areas of one or more types among logical storage areas of a plurality of types. As a source for an area to be assigned to the logical storage areas, a physical storage area which is common to the logical storage areas of the plurality of types is managed. Each CPU core, in the case of a data access to a logical storage area corresponding to the control rights of the CPU core, assigns an area required to store the data from the common physical storage area.

Abstract: A storage group configured by a plurality of storage devices is configured by a plurality of storage sub-groups, and the respective storage sub-groups are configured from two or more storage devices. A sub-group storage area, which is the storage area of the respective storage sub-groups, is configured by a plurality of rows of sub-storage areas. A data set, which is configured by a plurality of data elements configuring a data unit, and a second redundancy code created on the basis of this data unit, is written to a row of sub-storage areas, a compressed redundancy code is created on the basis of two or more first redundancy codes respectively created based on two or more data units of two or more storage sub-groups, and this compressed redundancy code is written to a nonvolatile storage area that differs from the above-mentioned two or more storage sub-groups.

Abstract: A first frequency dividing circuit and a second frequency dividing circuit are provided, and these circuits frequency-divide two-phase external clocks injected from an external part, to output four-phase clocks with phase guarantee. Each of the frequency dividing circuits includes a mixer, an adding circuit, and a phase circuit. The first frequency dividing circuit and the second frequency dividing circuit are coupled in loop shape via a first coupling circuit and a second coupling circuit. The first coupling circuit receives a first output signal of the first frequency dividing circuit to output a second external input signal to the second frequency dividing circuit, and the second coupling circuit receives a second output signal of the second frequency dividing circuit to output a first external input signal to the first frequency dividing circuit, and a clock frequency dividing circuit with a high loop gain and a wide lock range can be realized.

Abstract: LC resonant voltage control oscillators are adopted as voltage control oscillators for the purpose of providing a clock generating and distributing apparatus that can generate and distribute a clock signal of high precision even in a high-frequency region of several giga hertz or higher, and of providing a distributive VCO-type clock generating and distributing apparatus in which voltage control oscillators oscillate in the same phase, and which can generate a clock signal of a desired frequency and distributes a high-frequency clock signal to each part within a chip more stably even in a high-frequency region reaching 20 GHz. Furthermore, an inductor component of a wire connecting the oscillation nodes of the oscillators is made relatively small, or the LC resonant oscillators are oscillated in synchronization by using injection locking, whereby the LC resonant voltage control oscillators stably oscillate in the same phase.

Abstract: Optimum load distribution processing is selected and executed based on settings made by a user in consideration of load changes caused by load distribution in a plurality of asymmetric cores. A controller having a plurality of cores extracts, for each LU, a pattern showing the relationship between a core having an LU ownership and a candidate core as an LU ownership change destination based on LU ownership management information; measures, for each LU, the usage of a plurality of resources; predicates, for each LU based on the measurement results, a change in the usage of the plurality of resources and overhead to be generated by transfer processing itself; selects, based on the respective prediction results, a pattern that matches the user's setting information; and transfer the LU ownership to the core belonging to the selected pattern.

Abstract: A working machine (1) includes a frame (3), a body section (2) mounted to the frame (3) for pivotal movement about a vertical axis, a boom unit (7) having a plurality of booms, including a basal boom (7a), telescopically extendable from and retractable to one another. A support arm (14) is mounted to the body section (2) for pivotal movement about a horizontal axis. An end of the support arm (14) is coupled with the basal boom (7a). The basal boom (7a) is pivotable relative to the support arm (14) about a horizontal axis. A first hydraulically operable device extends from the body section (2) to the basal boom (7a) for pivoting the basal boom (7a) relative to the support arm (14) about the horizontal axis.

Abstract: In order to manage the various types of attribute information within the storage system, the storage system includes the following databases within a file-access controlling memory: a database for managing index information for managing contents of the files, and an index retrieval program, a database for managing the attribute information on the files, and a database for managing storage positions of blocks configuring a file. When the storage system receives an access request to a file, the utilization of these databases allows the storage system to make the access to the access-target file.

Abstract: There are provided a peaking detection part detecting a peaking amount in an output part of an inductor peaking circuit and a control signal generation part varying a circuit parameter of the inductor peaking circuit based on the peaking amount detected by the peaking detection part. Particularly, the inductor peaking circuit has inductors and resistors inserted in series between the output part and a power supply, and capacitances coupled in parallel between the output part and an earth (GND), and depending on respective values of these inductors, resistors and capacitances, it is possible to suppress a peaking generated in the output part.

Abstract: Provided is an information system for preserving data of a storage device in a computer that repeats the connection to and disconnection from a communication network. The computer acquires data to be written into the storage device and manages the update status of the storage device, transfers the data written into the storage device to the storage controller independent from the writing of data into the storage device when the computer is in a communicable state with the storage controller, and discontinues the transfer of data written into the storage device to the storage controller and manages the transfer status when the computer is not in a communicable state with the storage controller.

Abstract: A subject of the invention is to propose a storage subsystem assuring high reliability and not impairing processing performance. The invention is a storage subsystem which includes a storage device including a hard disk drive and a controller for controlling an access to the storage device in response to a predetermined access command transmitted from a host computer. The storage subsystem stores, in response to a write request transmitted from the host computer, data associated with the write request together with its parity in the storage device as well as verifies the validity of the data stored in the storage device independently of a response to the write request and, when there is an abnormality in the data, repairs the abnormal data.

Abstract: In order to provide a timing adjustment circuit capable of transmitting/receiving data without being affected by process unevenness and power voltage/temperature fluctuations even at a high data transfer rate, the phase of data outputted by a data transmitting unit is compared with the phase of a clock for regulating a data receiving timing of a data receiving unit, and the phase of a clock for regulating a data transmitting timing of the data transmitting unit is adjusted according to the comparison result.

Abstract: Provided is a storage subsystem that can reflect, when merging storage update information and local update information, those two kinds of update information in relevant volumes without overlapping the storage update information and the local update information. When reflecting update information in a storage subsystem 10 and update information in a mobile terminal 14 in relevant volumes, the storage subsystem 10: compares local update information and storage update information based on bitmaps; when both the relevant storage destinations overlap, selects a volume update pattern serving as a storage destination different from the storage destination for the local update information from among plural volume update patterns; and stores the storage update information in a storage area corresponding to the selected volume update pattern, and the mobile terminal 14 stores the storage update information in local storage 102.

Abstract: To reduce the performance degradation of storage system, this invention provides a storage system comprising a disk drive and a disk controller. The disk controller provides a storage area of the disk drive to a host computer; executes a processing of switching an encryption key that is used to encrypt data stored in the logical volume from a first encryption key to a second encryption key; encrypts write data requested to be written with the second encryption key when the write request for one of storage areas within the logical volume that stores data for which switching of encryption keys has not been finished is received while the encryption key switching processing is being executed; and writes the encrypted write data in the logical volume to switch encryption keys for data stored in the storage area where the data is requested to be written by the received write request.

Abstract: This storage system includes a plurality of data drives, a plurality of spare drives for storing data stored in at least one data drive among the plurality of data drives as save-target data, one or more RAID groups configured from the plurality of data drives, one or more spare RAID groups associated with the one or more RAID groups and configured from the plurality of spare drives, and a write unit to configured to write the save-target data into the plurality of spare drives configuring the one or more spare RAID groups in the order that the save-target data was read from the at least one data drive.

Abstract: A computer system includes a host computer; a first storage system that processes an I/O request issued by the host computer; and a second storage system that receives host I/O information and performance information from the first storage system and reproduces, based on the host I/O information and performance information, the internal processing conditions of the first storage system at the time the I/O request was processed, thereby simulating the I/O performance of the first storage system.