Semiconductor device
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Description
FIG. 1 is a front, top and right side perspective view of a semiconductor device, showing our new design;
FIG. 2 is a front elevational view thereof;
FIG. 3 is a rear elevational view thereof;
FIG. 4 is a top plan view thereof;
FIG. 5 is a bottom plan view thereof;
FIG. 6 is a right side elevational view thereof; and,
FIG. 7 is a left side elevational view thereof.
Claims
The ornamental design for a semiconductor device, as shown and described.
Referenced Cited
U.S. Patent Documents
Other references
5369551 | November 29, 1994 | Gore et al. |
D357672 | April 25, 1995 | Terasawa et al. |
D389808 | January 27, 1998 | Yamada et al. |
D396450 | July 28, 1998 | Nishiura et al. |
D396847 | August 11, 1998 | Nakayama et al. |
5991162 | November 23, 1999 | Saso |
D453746 | February 19, 2002 | Kato et al. |
6355877 | March 12, 2002 | Watanabe |
- J. Yamada, et al., “Next Generation High Power Dual IGBT Module with CSTBT Chip and New Packgage Concept”, Official Proceedings International Conferences ZM Communications GmbH, PCIM 2002, Power Electronics, May 14-16, 2002, 11 pages.
Patent History
Patent number: D476959
Type: Grant
Filed: Jul 31, 2002
Date of Patent: Jul 8, 2003
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo)
Inventors: Junji Yamada (Tokyo), Seiji Saiki (Fukuoka)
Primary Examiner: Ted Shooman
Assistant Examiner: Selina Sikder
Attorney, Agent or Law Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Application Number: 29/164,710
Type: Grant
Filed: Jul 31, 2002
Date of Patent: Jul 8, 2003
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo)
Inventors: Junji Yamada (Tokyo), Seiji Saiki (Fukuoka)
Primary Examiner: Ted Shooman
Assistant Examiner: Selina Sikder
Attorney, Agent or Law Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Application Number: 29/164,710
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)
International Classification: 1303;
International Classification: 1303;