Patents by Inventor Junji Yano

Junji Yano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10558360
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: February 11, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
  • Publication number: 20190347016
    Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.
    Type: Application
    Filed: July 23, 2019
    Publication date: November 14, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Junji YANO, Hidenori Matsuzaki, Kosuke Hatsuda
  • Patent number: 10379762
    Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: August 13, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
  • Publication number: 20190196723
    Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.
    Type: Application
    Filed: March 5, 2019
    Publication date: June 27, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Junji YANO, Hidenori MATSUZAKI, Kosuke HATSUDA
  • Publication number: 20180373447
    Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.
    Type: Application
    Filed: August 31, 2018
    Publication date: December 27, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Junji YANO, Hidenori MATSUZAKI, Kosuke HATSUDA
  • Patent number: 10067698
    Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: September 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
  • Publication number: 20180165011
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Application
    Filed: February 13, 2018
    Publication date: June 14, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
  • Patent number: 9933941
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: April 3, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
  • Publication number: 20170131929
    Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.
    Type: Application
    Filed: January 24, 2017
    Publication date: May 11, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Junji YANO, Hidenori MATSUZAKI, Kosuke HATSUDA
  • Patent number: 9582370
    Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: February 28, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
  • Publication number: 20170010818
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Application
    Filed: September 20, 2016
    Publication date: January 12, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuya KITSUNAI, Shinichi KANNO, Hirokuni YANO, Toshikatsu HIDA, Junji YANO
  • Patent number: 9483192
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: November 1, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
  • Patent number: 9417799
    Abstract: A memory system includes a nonvolatile semiconductor memory having blocks, the block being data erasing unit; and a controller configured to execute; an update processing for; writing superseding data in a block, the superseding data being treated as valid data; and invalidating superseded data having the same logical address as the superseding data, the superseded data being treated as invalid data; and a compaction processing for; retrieving blocks having invalid data using a management table, the management table managing blocks in a linked list format for each number of valid data included in the block; selecting a compaction source block having at least one valid data from the retrieved blocks; copying a plurality of valid data included in the compaction source blocks into a compaction target block; invalidating the plurality of valid data in the compaction source blocks; and releasing the compaction source blocks in which all data are invalidated.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: August 16, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Junji Yano, Kosuke Hatsuda, Hidenori Matsuzaki, Wataru Okamoto
  • Patent number: 9324653
    Abstract: On a single semiconductor package PK1, m semiconductor chips CP1 to CPm are mounted, and the semiconductor package PK1 has external terminals T shared by m pad electrodes PD1 to PDm of the m semiconductor chips CP1 to CPm. An electrostatic protection circuit CD is mounted on only one CPm of the m semiconductor chips CP1 to CPm.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: April 26, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigehiro Asano, Shinichi Kanno, Junji Yano
  • Patent number: 9280292
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: March 8, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
  • Publication number: 20160062675
    Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.
    Type: Application
    Filed: October 26, 2015
    Publication date: March 3, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Junji YANO, Hidenori MATSUZAKI, Kosuke HATSUDA
  • Publication number: 20160055080
    Abstract: A memory system according to an embodiment of the present invention comprises: speed of processing for searching through management tables is increased by providing a forward lookup table for searching for, respectively in track and cluster units, from a logical address, a storage device position where data corresponding to the logical address and a reverse lookup table for searching for, from a position of the storage device, a logical address stored in the position and linking these tables.
    Type: Application
    Filed: November 5, 2015
    Publication date: February 25, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Junji YANO, Kosuke HATSUDA, Hidenori MATSUZAKI
  • Publication number: 20160041767
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Application
    Filed: October 26, 2015
    Publication date: February 11, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuya KITSUNAI, Shinichi KANNO, Hirokuni YANO, Toshikatsu HIDA, Junji YANO
  • Publication number: 20160019113
    Abstract: A memory system includes a controlling unit that configured to control data transfer between the first and the second memory. The controlling unit executes copy processing for, after reading out data stored in a first page of the second memory to the first memory, writing the data in a second page of the second memory, determines, when executing the copy processing, whether the error correction processing for the data read out from the first page is successful, stores, when the error correction processing is successful, corrected data in the first memory and writes the corrected data in the second page, and reads out, when the error correction processing is unsuccessful, the data from the first page to the first memory and writes the data not subjected to the error correction processing in the second page.
    Type: Application
    Filed: September 28, 2015
    Publication date: January 21, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Junji YANO, Hidenori Matsuzaki, Kosuke Hatsuda, Hiroki Matsudaira
  • Publication number: 20150370646
    Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.
    Type: Application
    Filed: September 1, 2015
    Publication date: December 24, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Junji YANO, Hidenori Matsuzaki, Kosuke Hatsuda