Patents by Inventor Junji Yano
Junji Yano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8738867Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit stores management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of the management information in a latest state and a first pointer indicating a storage position of the second pointer. The first pointer is stored in a fixed area in the second storing unit and the second pointer is stored in an area excluding the fixed area in the second storing unit.Type: GrantFiled: April 2, 2013Date of Patent: May 27, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda, Shigehiro Asano, Shinichi Kanno, Toshikatsu Hida
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Publication number: 20140136772Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory include a first area, and a second area smaller than the first area; and a controller configured to control data stored in the nonvolatile semiconductor memory, wherein the nonvolatile semiconductor memory is configured to store a first data accessible by a host command and to a second data inaccessible by the host command, and when receiving the host command, the controller writes the second data of the first area within the second area and initializes a first address information related the first data.Type: ApplicationFiled: January 23, 2014Publication date: May 15, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji YANO, Hidenori MATSUZAKI, Kosuke HATSUDA
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Publication number: 20140122782Abstract: A memory system includes a first, second and third storing area included in a volatile semiconductor memory, and a controller that allocates the storage area of the nonvolatile semiconductor memory to the second storing area and the third storing area in a logical block unit associated with one or more blocks. First and second management units respectively manage the second and third storing areas. The second management unit has a size larger than that of the first management unit. When flushing data from the first to the second or third storing areas, the controller collects, from at least one of the first, second and third storing areas, data other than the data to be flushed and controls the flushing of the data such that a total of the data is a natural number times as large as the block unit as much as possible.Type: ApplicationFiled: November 1, 2013Publication date: May 1, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Junji YANO, Hidenori Matsuzaki, Kosuke Hatsuda
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Patent number: 8706950Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.Type: GrantFiled: February 27, 2009Date of Patent: April 22, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
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Publication number: 20140082345Abstract: On a single semiconductor package PK1, m semiconductor chips CP1 to CPm are mounted, and the semiconductor package PK1 has external terminals T shared by m pad electrodes PD1 to PDm of the m semiconductor chips CP1 to CPm. An electrostatic protection circuit CD is mounted on only one CPm of the m semiconductor chips CP1 to CPm.Type: ApplicationFiled: November 20, 2013Publication date: March 20, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Shigehiro ASANO, Shinichi KANNO, Junji YANO
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Patent number: 8677059Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory include a first area, and a second area smaller than the first area; and a controller configured to control data stored in the nonvolatile semiconductor memory, wherein the nonvolatile semiconductor memory is configured to store a first data accessible by a host command and to a second data inaccessible by the host command, and when receiving the host command, the controller writes the second data of the first area within the second area and initializes a first address information related the first data.Type: GrantFiled: March 1, 2013Date of Patent: March 18, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
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Patent number: 8661191Abstract: A memory system according to an embodiment of the present invention comprises: a data managing unit 120 is divided into a DRAM-layer managing unit 120a, a logical-NAND-layer managing unit 120b, and a physical-NAND-layer managing unit 120c to independently perform management of a DRAM layer, a logical NAND layer, and a physical NAND layer using the respective managing units to thereby perform efficient block management.Type: GrantFiled: January 26, 2012Date of Patent: February 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Junji Yano, Kosuke Hatsuda, Hidenori Matsuzaki
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Publication number: 20140040664Abstract: A method of controlling a nonvolatile semiconductor memory includes patrolling a first pool including a plurality of blocks/units with a first frequency, and when a first block/unit in the first pool satisfies a first condition, assigning the first block/unit to a second pool. The method includes patrolling the second pool with a second frequency, the second frequency being higher than the first frequency, and when a second block/unit in the second pool satisfies a second condition, moving data stored in the second block/unit to a free block/unit.Type: ApplicationFiled: October 9, 2013Publication date: February 6, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Toshikatsu Hida, Shinichi Kanno, Hirokuni Yano, Kazuya Kitsunai, Shigehiro Asano, Junji Yano
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Publication number: 20140013043Abstract: A memory system according to an embodiment of the present invention comprises: speed of processing for searching through management tables is increased by providing a forward lookup table for searching for, respectively in track and cluster units, from a logical address, a storage device position where data corresponding to the logical address and a reverse lookup table for searching for, from a position of the storage device, a logical address stored in the position and linking these tables.Type: ApplicationFiled: September 9, 2013Publication date: January 9, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji YANO, Kosuke HATSUDA, Hidenori MATSUZAKI
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Patent number: 8611154Abstract: On a single semiconductor package PK1, m semiconductor chips CP1 to CPm are mounted, and the semiconductor package PK1 has external terminals T shared by m pad electrodes PD1 to PDm of the m semiconductor chips CP1 to CPm. An electrostatic protection circuit CD is mounted on only one CPm of the m semiconductor chips CP1 to CPm.Type: GrantFiled: September 22, 2008Date of Patent: December 17, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Shigehiro Asano, Shinichi Kanno, Junji Yano
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Patent number: 8601219Abstract: A memory system includes a first storing area included in a volatile semiconductor memory, a second and a third storing area included in a nonvolatile semiconductor memory, a controller that allocates the storage area of the nonvolatile semiconductor memory to the second storing area and the third storing area in a logical block unit associated with one or more blocks. The second storing area is configured to be managed with a first management unit. The third storing area is configured to be managed with a second management unit, a size of the second management unit being larger than a size of the first management unit.Type: GrantFiled: March 12, 2009Date of Patent: December 3, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
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Patent number: 8583972Abstract: A method of controlling a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing, includes determining a monitored block as a candidate for refresh operation from among the plurality of blocks based on a predetermined condition. The method includes monitoring an error count of data stored in the monitored block and not monitoring an error count of data stored in blocks excluding the monitored block among the plurality of blocks. The method also includes performing the refresh operation on data stored in the monitored block in which the error count is larger than a first threshold value.Type: GrantFiled: June 1, 2012Date of Patent: November 12, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Toshikatsu Hida, Shinichi Kanno, Hirokuni Yano, Kazuya Kitsunai, Shigehiro Asano, Junji Yano
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Publication number: 20130290659Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit stores management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of the management information in a latest state and a first pointer indicating a storage position of the second pointer. The first pointer is stored in a fixed area in the second storing unit and the second pointer is stored in an area excluding the fixed area in the second storing unit.Type: ApplicationFiled: April 2, 2013Publication date: October 31, 2013Inventors: Junji YANO, Hidenori Matsuzaki, Kosuke Hatsuda, Shigehiro Asano, Shinichi Kanno, Toshikatsu Hida
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Patent number: 8554984Abstract: A memory system in which speed of processing for searching through management tables is increased by providing a forward lookup table for searching for, respectively in track and cluster units, from a logical address, a storage device position where data corresponds to the logical address, and a reverse lookup table for searching for, from a position of the storage device, a logical address stored in the position. These forward and reverse lookup tables are linked.Type: GrantFiled: February 10, 2009Date of Patent: October 8, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Junji Yano, Kosuke Hatsuda, Hidenori Matsuzaki
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Patent number: 8447914Abstract: A memory system according to an embodiment of the present invention comprises: a memory amount required for management table creation is reduced by adopting a nonvolatile semiconductor memory including a plurality of parallel operation elements respectively having a plurality of physical blocks as units of data erasing and a controller that can drive the parallel operation elements in parallel and has a number-of-times-of-erasing managing unit that manages the number of times of erasing in logical block units associated with a plurality of physical blocks driven in parallel.Type: GrantFiled: February 10, 2009Date of Patent: May 21, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Junji Yano, Kosuke Hatsuda, Hidenori Matsuzaki, Toshikatsu Hida
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Patent number: 8443133Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.Type: GrantFiled: February 10, 2009Date of Patent: May 14, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
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Patent number: 8438343Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of the data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit has a management information storage area for storing management information storage information including management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of management information in a latest state in the management information storage area and a first pointer indicating a storage position of the second pointer.Type: GrantFiled: February 10, 2009Date of Patent: May 7, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda, Shigehiro Asano, Shinichi Kanno, Toshikatsu Hida
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Patent number: 8433882Abstract: According to one embodiment, a disk array control device manages a plurality of drives as a single logical drive. The disk array control device includes a first register configured to store a to-be-accessed drive number which is designated by a host, and a control module. The control module is configured to receive a command from the host, determine whether the received command is a predetermined command which is used for maintenance of each of the drives, and execute, in a case where the received command is the predetermined command, a pass-through process of sending the received command to the drive which is designated by the to-be-accessed drive number in the first register.Type: GrantFiled: June 9, 2011Date of Patent: April 30, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Takehiko Kurashige, Junji Yano
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Patent number: 8429333Abstract: A controller includes an identification information management table that manages identification information indicating, for each of addresses in second-management unit, whether one or more data in first management unit belonging to the addresses is stored in the second or the third storing area. When the controller executes a process of flushing data from the first storing area to the second storing area or the third storing area, the controller updates the identification information in the identification information management table. The controller executes a process of reading data from the second storing area or the third storing area by referring to the identification information. As a result, the speed of searches conducted in the management table is increased.Type: GrantFiled: February 27, 2009Date of Patent: April 23, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Junji Yano, Kosuke Hatsuda, Hidenori Matsuzaki
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Patent number: 8407402Abstract: A memory system includes a management table group in which management information including storage positions of data stored in a first storing area and a second storing area is stored. The management table group is stored in the second storing area. A controller performs data transfer between a host apparatus and the second storing area via the first storing area and performs management of the data in the first and second storing areas based on the management table group while updating the management table group expanded in the first storing area. The second storing area can store data associated with a first logical address area accessible from the host apparatus and data associated with a second logical address area accessible from the host apparatus, and the controller receives an erasing command from the host apparatus, collects the data associated with the second logical address area in a predetermined area in the second storing area, and then initializes the management table group.Type: GrantFiled: February 27, 2009Date of Patent: March 26, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda