Patents by Inventor Junko Izumitani
Junko Izumitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20090001508Abstract: A semiconductor device includes a lower-layer substrate, a fuse above the lower-layer substrate and blown by radiation with light, a silicon oxide film on the fuse and on an exposed portion of the surface of the lower-layer substrate, and a silicon nitride film on the silicon oxide film. The portion of the silicon oxide film on the surface of the lower-layer substrate is thicker than the fuse, and the silicon oxide film has an opening opposite the fuse.Type: ApplicationFiled: August 6, 2008Publication date: January 1, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Noriaki Fujiki, Takashi Yamashita, Junko Izumitani
-
Patent number: 7423301Abstract: A semiconductor device includes a lower-layer substrate, a fuse above the lower-layer substrate and blown by radiation with light, a silicon oxide film on the fuse and on an exposed portion of the surface of the lower-layer substrate, and a silicon nitride film on the silicon oxide film. The portion of the silicon oxide film on the surface of the lower-layer substrate is thicker than the fuse, and the silicon oxide film has an opening opposite the fuse.Type: GrantFiled: April 9, 2007Date of Patent: September 9, 2008Assignee: Renesas Technology Corp.Inventors: Noriaki Fujiki, Takashi Yamashita, Junko Izumitani
-
Patent number: 7335537Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film supported by a semiconductor substrate, forming an aluminum layer supported by the first insulating film, etching the aluminum layer to form a bonding pad and fuse elements, depositing by plasma chemical vapor deposition a second insulating film covering the bonding pad and the fuse elements, the second insulating film having planar portions between the fuse elements and ridged portions opposite the fuse elements, depositing by plasma chemical vapor deposition a third insulating film covering the second insulating film, etching the third insulating film to form a first hole exposing a first region of the second insulating film, opposite the fuse elements, and a second hole exposing a second region of the second insulating film, opposite at least part of said bonding pad, and etching the second insulating film to form a third hole exposing at least part of the bonding pad.Type: GrantFiled: April 9, 2007Date of Patent: February 26, 2008Assignee: Renesas Technology Corp.Inventors: Noriaki Fujiki, Takashi Yamashita, Junko Izumitani
-
Publication number: 20070176257Abstract: A semiconductor device includes a lower-layer substrate, a fuse above the lower-layer substrate and blown by radiation with light, a silicon oxide film on the fuse and on an exposed portion of the surface of the lower-layer substrate, and a silicon nitride film on the silicon oxide film. The portion of the silicon oxide film on the surface of the lower-layer substrate is thicker than the fuse, and the silicon oxide film has an opening opposite the fuse.Type: ApplicationFiled: April 9, 2007Publication date: August 2, 2007Applicant: RENESAS TECHNOLOGY CORP.Inventors: Noriaki FUJIKI, Takashi YAMASHITA, Junko IZUMITANI
-
Publication number: 20070176258Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film supported by a semiconductor substrate, forming an aluminum layer supported by the first insulating film, etching the aluminum layer to form a bonding pad and fuse elements, depositing by plasma chemical vapor deposition a second insulating film covering the bonding pad and the fuse elements, the second insulating film having planar portions between the fuse elements and ridged portions opposite the fuse elements, depositing by plasma chemical vapor deposition a third insulating film covering the second insulating film, etching the third insulating film to form a first hole exposing a first region of the second insulating film, opposite the fuse elements, and a second hole exposing a second region of the second insulating film, opposite at least part of said bonding pad, and etching the second insulating film to form a third hole exposing at least part of the bonding pad.Type: ApplicationFiled: April 9, 2007Publication date: August 2, 2007Applicant: RENESAS TECHNOLOGY CORP.Inventors: Noriaki FUJIKI, Takashi YAMASHITA, Junko IZUMITANI
-
Patent number: 7217965Abstract: A semiconductor device includes a lower-layer substrate, a fuse above the lower-layer substrate and blown by radiation with light, a silicon oxide film on the fuse and on an exposed portion of the surface of the lower-layer substrate, and a silicon nitride film on the silicon oxide film. The portion of the silicon oxide film on the surface of the lower-layer substrate is thicker than the fuse, and the silicon oxide film has an opening opposite the fuse.Type: GrantFiled: December 11, 2003Date of Patent: May 15, 2007Assignee: Renesas Technology Corp.Inventors: Noriaki Fujiki, Takashi Yamashita, Junko Izumitani
-
Patent number: 6890857Abstract: The present invention provides a semiconductor device which can prevent the oxidization of the surfaces of pad electrodes to enhance the connecting strength between the pad electrodes and external terminals. The semiconductor device according to the present invention comprises pad electrodes for use in connecting external electrodes and a multilayer wiring structure connected to the pad electrodes, wherein one surface of an insulating layer covering the pad electrodes and having openings over the pad electrodes for exposing the surfaces of the pad electrodes is in contact with a metal layer formed from one selected from precious metals and alloys containing the precious metals as main components.Type: GrantFiled: October 28, 2002Date of Patent: May 10, 2005Assignee: Renesas Technology Corp.Inventors: Shigeru Harada, Yoshifumi Takata, Junko Izumitani
-
Publication number: 20040195648Abstract: A semiconductor device includes a lower-layer substrate, a fuse above the lower-layer substrate and blown by radiation with light, a silicon oxide film on the fuse and on an exposed portion of the surface of the lower-layer substrate, and a silicon nitride film on the silicon oxide film. The portion of the silicon oxide film on the surface of the lower-layer substrate is thicker than the fuse, and the silicon oxide film has an opening opposite the fuse.Type: ApplicationFiled: December 11, 2003Publication date: October 7, 2004Applicant: Renesas Technology Corp.Inventors: Noriaki Fujiki, Takashi Yamashita, Junko Izumitani
-
Publication number: 20040157464Abstract: A manufacturing method of an electronic device having a wiring connection structure which can prevent a loose connection between a via plug and a metal wiring is obtained. In an etching process to form a via hole (8), a mixed gas of C4H8, O2 and Ar is employed as an etching gas. According to this, a surface of a side wall of the via hole (8) has a smooth shape without a microscopic unevenness on an upper part of the side wall of the via hole (8) at least. Accordingly, a gap caused by the microscopic unevenness described above does not occur between a barrier metal film (9) and the side wall of the via hole (8), and both sides stick to each other. As a result, in a cleaning process employing a hydrofluoric acid after a CMP process, a cleaning solution does not penetrate a metal film (3) through the gap between the barrier metal film (9) and the side wall of the via hole (8).Type: ApplicationFiled: June 30, 2003Publication date: August 12, 2004Applicant: Renesas Technology Corp.Inventor: Junko Izumitani
-
Patent number: 6727590Abstract: A semiconductor device has a multilayer interconnection structure in which a plurality of interconnection layers is formed in an insulating film. The multilayer interconnection structure has a first metal film made of a first material and functioning as a first interconnection belonging to an interconnection layer other than an uppermost interconnection layer, a second metal film made of a second material and functioning as a second interconnection belonging to the uppermost interconnection layer, a third metal film made of the first material and belonging to an interconnection layer other than the uppermost interconnection layer and functioning as a bonding pad, an opening formed in the insulating film and having its bottom defined by the third metal film, and a bonding wire connected to the third metal film through the opening. The second material has a lower resistance and is more susceptible to oxidation than the first material.Type: GrantFiled: May 2, 2002Date of Patent: April 27, 2004Assignee: Renesas Technology Corp.Inventors: Junko Izumitani, Hiroki Takewaka
-
Publication number: 20040017279Abstract: The present invention protects a wiring against an etchant when a fuse connected to this wiring is subjected to a laser blow. A fuse has a barrier metal at its lower side. A plug is connected to the lower side of the fuse. The plug has a barrier metal at least at its lower side. Even if the fuse is partly removed through the laser blow at a region other than a portion where the fuse is connected to the plug, two layers of the barrier metals remain between the removed portion and a lower wiring. This enlarges the margin for preventing the adverse influence, such as corrosion and breaking of the lower wiring, brought by an etchant associated in other manufacturing process.Type: ApplicationFiled: January 24, 2003Publication date: January 29, 2004Applicants: MITSUBISHI DENKI KABUSHIKI KAISHA, Ryoden Semiconductor System Engineering Corp.Inventors: Takao Kamoshima, Junko Izumitani, Shigeki Sunada
-
Patent number: 6645863Abstract: The invention provides a method of manufacturing a semiconductor device which can reduce or prevent abrasive material from remaining in an indentation in a surface after a CMP process. After forming a titanium nitride film (5), a tungsten film (6) is formed on an entire surface. The temperature is set at approximately 430° C. for the reaction and, first, 50 sccm of WF6, 10 sccm of SiH4 and 1000 sccm of H2 are used in the atmosphere of 30 Torr of Ar, N2 so as to form a seed layer with a film thickness of approximately 100 nm. After that, in the atmosphere of 80 Torr of Ar, N2, 75 sccm of WF6 and 500 sccm of H2 are used as a reactive gas so as to layer a film with a thickness of approximately 300 nm. The tungsten film (6) has grains (6a) in a pillar form of which the grain diameter is small to the degree that the abrasive material (50) used in the CMP process does not easily become caught in the gaps between the grains.Type: GrantFiled: November 7, 2001Date of Patent: November 11, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiroki Takewaka, Takao Kamoshima, Junko Izumitani
-
Publication number: 20030109100Abstract: A dielectric layer for capacitive element is formed on a lower electrode. An interlayer insulating layer is formed on the lower electrode and the dielectric layer for capacitive element. A plug hole reaching the dielectric layer for capacitive element is formed in the interlayer insulating layer. Upper electrodes are formed to fill in the plug hole and positioned opposite to the lower electrode with the dielectric layer for capacitive element interposed. The dielectric layer for capacitive element is in contact with the upper surface of the lower electrode at a region directly below the plug hole and a region outside the sidewall of the plug hole. Thus, a semiconductor device having a capacitive element with a greater capacitance which prevents diffusion of metal atoms from the lower electrode as well as a manufacturing method thereof are provided.Type: ApplicationFiled: November 26, 2002Publication date: June 12, 2003Applicants: MITSUBISHI DENKI KABUSHIKI KAISHA, RYODEN SEMICONDUCTOR SYSTEM ENGINEERING CORPORATIONInventors: Yoshifumi Takata, Junko Izumitani, Shigeki Sunada
-
Publication number: 20030100177Abstract: Before polishing an insulating interlayer film by a CMP process, conductor plugs as erosion-inducing portions are formed on a convex surface of the film. Erosion occurs in the convex surface upon the CMP process, and the residual-free flat surface of insulating interlayer film can be obtained.Type: ApplicationFiled: July 30, 2002Publication date: May 29, 2003Inventors: Hiroki Takewaka, Noriaki Fujiki, Junko Izumitani
-
Publication number: 20030080428Abstract: A semiconductor device and its manufacturing method are obtained in which, in a semiconductor device having a multilayer interconnection structure using copper interconnections, a bonding wire can be bonded to a bonding pad with enhanced connecting reliability and stability. Third-layer interconnections (17) and a bonding pad (71), both made of an aluminum alloy, are formed partially on a second interlayer insulating film (14). An opening (74) whose bottom is defined by the bonding pad (71) is partially formed in a third interlayer insulating film (63), a fourth interlayer insulating film (67), a protective insulating film (72), and a buffer coat film (73). A bonding wire (75) is inserted in the opening (74) and bonded to the bonding pad (71).Type: ApplicationFiled: May 2, 2002Publication date: May 1, 2003Applicant: MITSUBISHI DENKI KABUSHIKIInventors: Junko Izumitani, Hiroki Takewaka
-
Publication number: 20030052339Abstract: The present invention provides a semiconductor device which can prevent the oxidization of the surfaces of pad electrodes to enhance the connecting strength between the pad electrodes and external terminals. The semiconductor device according to the present invention comprises pad electrodes for use in connecting external electrodes and a multilayer wiring structure connected to the pad electrodes, wherein one surface of an insulating layer covering the pad electrodes and having openings over the pad electrodes for exposing the surfaces of the pad electrodes is in contact with a metal layer formed from one selected from precious metals and alloys containing the precious metals as main components.Type: ApplicationFiled: October 28, 2002Publication date: March 20, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Shigeru Harada, Yoshifumi Takata, Junko Izumitani
-
Patent number: 6500675Abstract: A dielectric layer for capacitive element is formed on a lower electrode. An interlayer insulating layer is formed on the lower electrode and the dielectric layer for capacitive element. A plug hole reaching the dielectric layer for capacitive element is formed in the interlayer insulating layer. Upper electrodes are formed to fill in the plug hole and positioned opposite to the lower electrode with the dielectric layer for capacitive element interposed. The dielectric layer for capacitive element is in contact with the upper surface of the lower electrode at a region directly below the plug hole and a region outside the sidewall of the plug hole. Thus, a semiconductor device having a capacitive element with a greater capacitance which prevents diffusion of metal atoms from the lower electrode as well as a manufacturing method thereof are provided.Type: GrantFiled: April 19, 2001Date of Patent: December 31, 2002Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering CorporationInventors: Yoshifumi Takata, Junko Izumitani, Shigeki Sunada
-
Publication number: 20020177325Abstract: The invention provides a method of manufacturing a semiconductor device which can reduce or prevent abrasive material from remaining in an indentation in a surface after a CMP process.Type: ApplicationFiled: November 7, 2001Publication date: November 28, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Hiroki Takewaka, Takao Kamoshima, Junko Izumitani
-
Patent number: 6476491Abstract: The present invention provides a semiconductor device which can prevent the oxidization of the surfaces of pad electrodes to enhance the connecting strength between the pad electrodes and external terminals. The semiconductor device according to the present invention comprises pad electrodes for use in connecting external electrodes and a multilayer wiring structure connected to the pad electrodes, wherein one surface of an insulating layer covering the pad electrodes and having openings over the pad electrodes for exposing the surfaces of the pad electrodes is in contact with a metal layer. formed from one selected from precious metals and alloys containing the precious metals as main components.Type: GrantFiled: January 10, 2001Date of Patent: November 5, 2002Assignee: Mitsubishi Denki Kabushiki KaihsaInventors: Shigeru Harada, Yoshifumi Takata, Junko Izumitani
-
Patent number: 6476496Abstract: An interconnection forming step provides an interconnection with an improved yield, a low cost and a high reliability. A semiconductor device includes an insulating layer formed on a silicon substrate and having a groove extending in a predetermined direction. A distance between side walls defining insulating layer increases as a position moves away from silicon substrate. The semiconductor device includes a conductive layer filling groove.Type: GrantFiled: December 15, 1999Date of Patent: November 5, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Junko Izumitani