Patents by Inventor Junko Izumitani

Junko Izumitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020081836
    Abstract: There are provided a cell plate layer 5 formed in the insulating films 10 and 11 on a semiconductor substrate 4. A connecting hole 12 is formed through the insulating films 10 and 11 and the cell plate layer 5, and the circumference of the side surface of the cell plate layer is exposed. A conducting plug 7A is formed by filling the connecting hole 12 with a conductor so as to contact the circumference of the side surface, for example, an upper surface of the cell plate layer 5. By increasing a contact area between a conductor layer and a conducting member, a contact resistance is lowered, and a stable and reliable semiconductor device is obtained.
    Type: Application
    Filed: May 17, 2001
    Publication date: June 27, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Hiroki Takewaka, Takao Kamoshima, Junko Izumitani
  • Publication number: 20020074587
    Abstract: A dielectric layer for capacitive element is formed on a lower electrode. An interlayer insulating layer is formed on the lower electrode and the dielectric layer for capacitive element. A plug hole reaching the dielectric layer for capacitive element is formed in the interlayer insulating layer. Upper electrodes are formed to fill in the plug hole and positioned opposite to the lower electrode with the dielectric layer for capacitive element interposed. The dielectric layer for capacitive element is in contact with the upper surface of the lower electrode at a region directly below the plug hole and a region outside the sidewall of the plug hole. Thus, a semiconductor device having a capacitive element with a greater capacitance which prevents diffusion of metal atoms from the lower electrode as well as a manufacturing method thereof are provided.
    Type: Application
    Filed: April 19, 2001
    Publication date: June 20, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshifumi Takata, Junko Izumitani, Shigeki Sunada
  • Patent number: 6333259
    Abstract: Disclosed is an apparatus for manufacturing a semiconductor device including a metal film which is formed on a semiconductor substrate in a film formation region containing the interior of a hole formed in the semiconductor substrate. The apparatus includes a degassing chamber, a film forming chamber, and a cooing chamber. The degassing chamber 34 is provided for carrying out a degassing process by heating the semiconductor substrate to a degassing temperature. The film forming chamber 40 is provided for forming a metal film on the film formation region in a state in which the semiconductor substrate is heated to a film formation temperature. The cooling chamber 38 is provided for cooling, after completion of the degassing process and before beginning of the formation of the metal film, the semiconductor substrate to a cold temperature being lower than the film formation temperature and in a range of −50° C. to 150° C.
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: December 25, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Junko Izumitani, Kazuyoshi Maekawa
  • Publication number: 20010008311
    Abstract: The present invention provides a semiconductor device which can prevent the oxidization of the surfaces of pad electrodes to enhance the connecting strength between the pad electrodes and external terminals. The semiconductor device according to the present invention comprises pad electrodes for use in connecting external electrodes and a multilayer wiring structure connected to the pad electrodes, wherein one surface of an insulating layer covering the pad electrodes and having openings over the pad electrodes for exposing the surfaces of the pad electrodes is in contact with a metal layer formed from one selected from precious metals and alloys containing the precious metals as main components.
    Type: Application
    Filed: January 10, 2001
    Publication date: July 19, 2001
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigeru Harada, Yoshifumi Takata, Junko Izumitani
  • Patent number: 6016562
    Abstract: An ordinary user can easily learn a step at which a problem occurs during semiconductor manufacturing processes and improve the yield of manufacturing products and the quality of the products. At a certain in-line inspection step, a CPU (3) stores data signals (V1) taken by an inspection apparatus (1) into a memory (2), and reads a result (V6) obtained at a precedent step and stores the same in the memory (2). The CPU (3) reads stored data signals (V2) from the memory (2), performs comparison or referral on data about defects which are detected at a current step and the result (V6) regarding the precedent step, and generates a defect data analysis processing result signal (V5) regarding the current step. The result (V5) consists of disappeared defect data, common defect data, new defect data to which a label of a current step number is assigned, and reappeared defect data.
    Type: Grant
    Filed: August 28, 1997
    Date of Patent: January 18, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoko Miyazaki, Nobuyoshi Hattori, Junko Izumitani, Masahiko Ikeno