Patents by Inventor Junpei Kusukawa

Junpei Kusukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6730255
    Abstract: A method for manufacture of a resin block includes setting high-voltage and low-voltage side conductors in dies, assembling the dies, extruding resin so as to form a resin block having the high-voltage side conductor and the low-voltage side conductor embedded therein, cooling the molded resin block, and taking out the molded resin block from the dies.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: May 4, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Ryozo Takeuchi, Junpei Kusukawa, Koji Obata
  • Publication number: 20030218273
    Abstract: A method for manufacture of a resin block includes setting high-voltage and low-voltage side conductors in dies, assembling the dies, extruding resin so as to form a resin block having the high-voltage side conductor and the low-voltage side conductor embedded therein, cooling the molded resin block, and taking out the molded resin block from the dies.
    Type: Application
    Filed: June 17, 2003
    Publication date: November 27, 2003
    Inventors: Ryozo Takeuchi, Junpei Kusukawa, Koji Obata
  • Publication number: 20030213616
    Abstract: The present invention provides a printed wiring board which has high insulation resistance between wirings and is unlikely to cause failures such as leakages or short circuits, attributable to ion migration even in high temperatures and highly humid environments. The printed wiring board has a circuit comprising a metal conductor on base metal layers created by forming an insulating resin layer 4 on at least one face of an insulating substrate 1 and forming the base metal layers 2 and 5 on the insulating resin layer. In the printed wiring board, at least a part of an upper face of the insulating resin layer existing in spaces 11 between the metal conductors is formed at a position lower than the interface between the base metal layer 5 and the insulating resin layer 4.
    Type: Application
    Filed: May 15, 2003
    Publication date: November 20, 2003
    Inventors: Junpei Kusukawa, Ryozo Takeuchi
  • Patent number: 6649847
    Abstract: A resin block insulating system comprising a plurality of resin blocks laid so as to cover a high-voltage part. Each of the resin blocks has a side surface opposite to a side surface of an adjacent resin block via a gap formed therebetween. The side surfaces are substantially parallel with each other and extend in an inclined direction with reference to a thickness direction of the resin block insulating system so as to extend an insulation length of the gap.
    Type: Grant
    Filed: February 27, 2001
    Date of Patent: November 18, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Ryozo Takeuchi, Junpei Kusukawa, Koji Obata
  • Publication number: 20030052420
    Abstract: Described is a semiconductor device comprising a plurality of inner leads each made of copper or an alloy thereof; a heat sink made of copper or an alloy thereof, bonded to one end of each of a plurality of inner leads via an insulating adhesive layer and having a semiconductor element mounted on the heat sink via a metal wire; a plurality of metal wires each electrically connecting the semiconductor element and each of the plurality of inner leads; an encapsulating resin encapsulating the semiconductor element and the plurality of metal wires; and a plurality of outer leads protruded outside of the encapsulating resin and bent in the gullwing form. The encapsulating resin has been added with an additive forming a compound with an ionic impurity so that water at the peeling portion becomes near neutral, which prevents reaction and easy elution of copper, thereby preventing Cu migration.
    Type: Application
    Filed: August 22, 2002
    Publication date: March 20, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Hiromichi Suzuki, Akihiko Kameoka, Masaru Yamada, Takafumi Nishita, Fujio Ito, Junpei Kusukawa, Ryozo Takeuchi, Toshiaki Ishii
  • Publication number: 20030042597
    Abstract: In a semiconductor device which is assembled by making use of a lead frame 1 with a heat radiation plate 3 in which the lead frame 1 and the heat radiation plate 3 made of copper or copper alloy are joined by an adhesive layer 2 formed on a surface of the heat radiation plate 3 and at least a part of the inner leads 1a of the lead frame 1 is applied of a plating for a metallic fine wire connection, at least the entire portion where the lead frame 1 joins with the adhesive layer 2 is covered by at least one metal or alloy thereof different from the metallic fine wire connecting use plating selected from the group consisting of gold, platinum, iridium, rhodium, palladium, ruthenium, indium, tin, molybdenum, tungsten, gallium, zinc, chromium, niobium, tantalum, titanium and zirconium. Thereby, generation of inconveniences such as leakage and shorting due to ion migration can be prevented.
    Type: Application
    Filed: March 25, 2002
    Publication date: March 6, 2003
    Inventors: Junpei Kusukawa, Ryozo Takeuchi, Toshiaki Ishii, Hiromichi Suzuki, Fujio Ito, Takafumi Nishita, Akihiko Kameoka, Masaru Yamada
  • Patent number: 6504110
    Abstract: In order to restrict a local concentration of an electric field in a conductor layer end portion of an insulating circuit board and increase a partial electric discharge starting voltage, thereby improving an insulating reliability of the insulating circuit board and a power semiconductor apparatus employing the same, the present invention provides a method of manufacturing a insulating circuit board comprising the step of applying a voltage between the circuit patterns of the insulating circuit board in an atmospheric or depressurized gas so as to allow the circuit board to discharge electricity, or irradiating a laser beam, thereby a projection shape of the end portion of the electrode conductor is melted and smoothened so as to restrict the concentration of the electric field.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: January 7, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Junpei Kusukawa, Ryozo Takeuchi
  • Publication number: 20020027015
    Abstract: A resin is blocked to provide an electric insulating layer, which covers a high-voltage part densely, so that the electric insulating layer is easy to disassemble.
    Type: Application
    Filed: February 27, 2001
    Publication date: March 7, 2002
    Inventors: Ryozo Takeuchi, Junpei Kusukawa, Koji Obata