Abstract: A multicore processor may include a plurality of cores including at least a first core and a second core, a shared peripheral comprising a plurality of interrupt register banks including at least a first interrupt register bank dedicated to the first core and a second interrupt register bank dedicated to the second core, and a plurality of communications bridges, including at least a first bridge interfaced between the first core and the shared peripheral and at least a second bridge interfaced between the second core and the shared peripheral. The first core may be configured to program the first interrupt register bank via the first bridge to configure the shared peripheral for access by the first core. The second core may be configured to program the second interrupt register bank via the second bridge to configure the shared peripheral for access by the second core.

Abstract: A control method for a user interface system may include receiving an input signal, receiving a temperature signal indicative of a temperature, generating a baseline signal based on at least one among the input signal and the temperature signal, calculating an error signal based on a difference of the input signal and the baseline signal, and modifying the baseline signal based on the error signal.

Abstract: A control method for a user interface system may include receiving an input signal, receiving a temperature signal indicative of a temperature, generating a baseline signal based on at least one among the input signal and the temperature signal, calculating an error signal based on a difference of the input signal and the baseline signal, and modifying the baseline signal based on the error signal.

Abstract: A method may include receiving an input signal, generating a baseline signal based on the input signal, generating a corrected input signal by subtracting the baseline signal from the input signal, determining a threshold level change of the input signal when the corrected input signal exceeds a level change threshold, and responsive to the threshold level change, updating the baseline signal to the level change threshold.

Abstract: Sensing electronics may be used to measure capacitance of components, such as speakers in mobile devices. A sensing circuit may include a charge-sense front end with sine wave excitation, an analog-to-digital conversion block, and a digital demodulator. The component being measured by the sensing electronics may be excited by a high-frequency sine wave excitation. The digitization of the output from the component may be performed using a bandpass filter synchronized with the excitation signal by centering the bandpass filter near (e.g., within 5% of) the frequency of the excitation signal.

Abstract: In one embodiment, an apparatus includes: a first demodulator to demodulate a digital signal into a first demodulated audio signal; a second demodulator to demodulate an analog signal into a second demodulated audio signal, the first and second demodulated audio signals including common content; and a delay determination circuit to determine a delay value between the common content of the two demodulated audio signals based at least in part on a first delay estimate having a first resolution and a second delay estimate having a second resolution.

Abstract: In one aspect, a tuner includes an analog front end to receive a radio frequency (RF) signal and to downconvert the RF signal to a second frequency signal, a digitizer to convert the second frequency signal to a digitized signal, a channel equalizer including a filter to filter the digitized signal, and a first controller to update the filter according to a frequency response of the filter.

Abstract: In one embodiment, an apparatus includes: a first demodulator to demodulate a digital signal into a first demodulated audio signal; a second demodulator to demodulate an analog signal into a second demodulated audio signal, the first and second demodulated audio signals including common content; and a delay determination circuit to determine a delay value between the common content of the two demodulated audio signals based at least in part on a first delay estimate having a first resolution and a second delay estimate having a second resolution.

Abstract: Radio frequency (RF) receivers having whitened digital frame processing and related methods are disclosed. Disclosed embodiments whiten frequency domain interference generated periodic current pulses from by digital frame processing by applying a variable time delay to the frame control signals that initiate digital frame processing. For one embodiment, the variable time delay is achieved by waiting a variable number of digital clock cycles for each digital frame processing cycle. Still further, a variable number of no operation (NO-OP) cycles can be performed at the beginning of each frame processing cycle to provide the variable time delay for the variable number of digital clock cycles. Other variable time delay techniques could also be utilized while still taking advantage of the whitened digital frame processing embodiments described herein.

Abstract: Radio frequency (RF) receivers having whitened digital frame processing and related methods are disclosed. Disclosed embodiments whiten frequency domain interference generated periodic current pulses from by digital frame processing by applying a variable time delay to the frame control signals that initiate digital frame processing. For one embodiment, the variable time delay is achieved by waiting a variable number of digital clock cycles for each digital frame processing cycle. Still further, a variable number of no operation (NO-OP) cycles can be performed at the beginning of each frame processing cycle to provide the variable time delay for the variable number of digital clock cycles. Other variable time delay techniques could also be utilized while still taking advantage of the whitened digital frame processing embodiments described herein.

Abstract: In one aspect, a tuner includes an analog front end to receive a radio frequency (RF) signal and to downconvert the RF signal to a second frequency signal, a digitizer to convert the second frequency signal to a digitized signal, a channel equalizer including a filter to filter the digitized signal, and a first controller to update the filter according to a frequency response of the filter.

Abstract: In an embodiment, an apparatus includes a first signal path to receive and process a radio frequency (RF) signal of a first band and which has a first programmable digitizer to convert the RF signal of the first band into a digitized signal without downconversion. In addition, the apparatus further includes a second signal path to receive and process an RF signal of a second band, where at least portions of one or more of the paths may be shared during operation in the different bands.

Abstract: In an embodiment, an apparatus includes a first signal path to receive and process a radio frequency (RF) signal of a first band and which has a first programmable digitizer to convert the RF signal of the first band into a digitized signal without downconversion. In addition, the apparatus further includes a second signal path to receive and process an RF signal of a second band, where at least portions of one or more of the paths may be shared during operation in the different bands.

Abstract: In one embodiment, a method includes determining in a controller of a radio receiver whether at least one blocker signal is present in a blocking spectrum surrounding a desired radio channel. If no blocker signal is present, a channel filter of a signal processing path of the radio receiver may be controlled to operate at a first bandwidth. If a first blocker signal is present, the channel filter may be controlled to operate at a second bandwidth less than the first bandwidth. If the first blocker signal and a second blocker signal are present on opposing sides of the desired radio channel, the channel filter may be controlled to operate at a third bandwidth less than the second bandwidth, when a beating signal based on the first and second blocker signals is greater than a threshold level.

Abstract: In one embodiment, a method includes determining in a controller of a radio receiver whether at least one blocker signal is present in a blocking spectrum surrounding a desired radio channel. If no blocker signal is present, a channel filter of a signal processing path of the radio receiver may be controlled to operate at a first bandwidth. If a first blocker signal is present, the channel filter may be controlled to operate at a second bandwidth less than the first bandwidth. If the first blocker signal and a second blocker signal are present on opposing sides of the desired radio channel, the channel filter may be controlled to operate at a third bandwidth less than the second bandwidth, when a beating signal based on the first and second blocker signals is greater than a threshold level.

Abstract: One aspect of the present invention is directed to an apparatus to perform impulse blanking of a received signal at multiple locations of a signal processing path. To effect such impulse blanking, multiple impulse detectors and blankers may be present, in addition to other circuitry. The impulse detectors may operate at different bandwidths, and the impulse blankers may be located at different locations of the signal processing path and may be differently configured.

Abstract: In one embodiment, a method for processing radio frequency signals includes estimating an average value of a demodulated signal and a noise signal, both obtained from a radio frequency signal, estimating a noise floor based on the noise signal, generating a blend control signal based on the average values and the noise floor, and blending at least two path signals based on the blend control signal to obtain a blended signal. This blended signal may be output for further processing when multipath noise is detected.

Abstract: One aspect of the present invention is directed to an apparatus to perform impulse blanking of a received signal at multiple locations of a signal processing path. To effect such impulse blanking, multiple impulse detectors and blankers may be present, in addition to other circuitry. The impulse detectors may operate at different bandwidths, and the impulse blankers may be located at different locations of the signal processing path and may be differently configured.

Abstract: In one embodiment, a receiver includes parallel paths for signal channel processing and image channel processing. The paths may include a mixer to receive an intermediate frequency (IF) signal and to downconvert the IF signal to a channel baseband signal, a filter to generate a filtered channel value, a combiner to combine the channel baseband signal with a filtered channel value from the other path to obtain a channel path output, in addition to one or more controllers to generate a step control signal and update a weighting of the filters based at least in part on the step control signal.

Abstract: One aspect of the present invention is directed to an apparatus to perform impulse blanking of a received signal at multiple locations of a signal processing path. To effect such impulse blanking, multiple impulse detectors and blankets may be present, in addition to other circuitry. The impulse detectors may operate at different bandwidths, and the impulse blankers may be located at different locations of the signal processing path and may be differently configured.