Patents by Inventor Justin Brask

Justin Brask has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Controlled use of photochemically susceptible chemistries for etching, cleaning and surface conditioning
    Publication number: 20060108067
    Abstract: Radiant energy may be applied to a photochemically susceptible etching or conditioning solution to enable precise control of the removal of material or alteration of the top surface of a wafer during the fabrication of semiconductor integrated circuits. A particular condition may be detected during the course of photoactivated generation of free radicals or molecular activation to control the further generation of said species by controlling the radiant energy exposure of a wafer.
    Type: Application
    Filed: January 9, 2006
    Publication date: May 25, 2006
    Inventors: Subramanyam Iyer, Justin Brask, Vijayakumar Ramachandrarao
  • Method for making a semiconductor device with a high-k gate dielectric layer and a silicide gate electrode
    Publication number: 20060094180
    Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, forming a barrier layer on the high-k gate dielectric layer, and forming a fully silicided gate electrode on the barrier layer.
    Type: Application
    Filed: November 2, 2004
    Publication date: May 4, 2006
    Inventors: Mark Doczy, Justin Brask, Jack Kavalieros, Matthew Metz, Suman Datta, Robert Chau
  • Resonant tunneling device using metal oxide semiconductor processing
    Publication number: 20060091467
    Abstract: An embodiment of the present invention is a technique to fabricate a semiconductor device having low off state leakage current. A gate structure of a first device is formed on a substrate layer having a hardmask. A channel is formed underneath the gate structure having a width to support the gate structure. An oxide or a dielectric layer is deposited on the substrate layer. A doped polysilicon layer is deposited on the oxide layer. A recessed junction area is formed on the doped polysilicon layer between the first device and an adjacent device.
    Type: Application
    Filed: October 29, 2004
    Publication date: May 4, 2006
    Inventors: Brian Doyle, Suman Datta, Justin Brask, Jack Kavalieros, Amlan Majumdar, Marko Radosavljevic, Robert Chan
  • Method for making a semiconductor device with a high-k gate dielectric layer and a silicide gate electrode
    Publication number: 20060091483
    Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, forming a barrier layer on the high-k gate dielectric layer, and forming a fully silicided gate electrode on the barrier layer.
    Type: Application
    Filed: October 3, 2005
    Publication date: May 4, 2006
    Inventors: Mark Doczy, Justin Brask, Jack Kavalieros, Matthew Metz, Suman Datta, Robert Chau
  • Nonplanar device with thinned lower body portion and method of fabrication
    Publication number: 20060086977
    Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Application
    Filed: October 25, 2004
    Publication date: April 27, 2006
    Inventors: Uday Shah, Brian Doyle, Justin Brask, Robert Chau, Thomas Letson
  • Method for making a semiconductor device having a high-k gate dielectric
    Publication number: 20060079005
    Abstract: A method for making a semiconductor device is described. That method comprises converting a hydrophobic surface of a substrate into a hydrophilic surface, and forming a high-k gate dielectric layer on the hydrophilic surface.
    Type: Application
    Filed: October 12, 2004
    Publication date: April 13, 2006
    Inventors: Justin Brask, Jack Kavalieros, Mark Doczy, Matthew Metz, Suman Datta, Robert Chau
  • Nonplanar transistors with metal gate electrodes
    Publication number: 20060071275
    Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Application
    Filed: September 30, 2004
    Publication date: April 6, 2006
    Inventors: Justin Brask, Brian Doyle, Jack Kavalieros, Mark Doczy, Uday Shah, Robert Chau
  • Inducing strain in the channels of metal gate transistors
    Publication number: 20060071285
    Abstract: In a metal gate replacement process, strain may be selectively induced in the channels of NMOS and PMOS transistors. For example, a material having a higher coefficient of thermal expansion than the substrate may be used to form the gate electrodes of PMOS transistors. A material with a lower coefficient of thermal expansion than that of the substrate may be used to form the gate electrodes of NMOS transistors.
    Type: Application
    Filed: September 29, 2004
    Publication date: April 6, 2006
    Inventors: Suman Datta, Jack Kavalieros, Mark Doczy, Matthew Metz, Justin Brask, Robert Chau, Brian Doyle
  • Fabrication of channel wraparound gate structure for field-effect transistor
    Publication number: 20060068591
    Abstract: A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.
    Type: Application
    Filed: September 29, 2005
    Publication date: March 30, 2006
    Inventors: Marko Radosavljevic, Amlan Majumdar, Suman Datta, Jack Kavalieros, Brian Doyle, Justin Brask, Robert Chau
  • Processing electronic devices using a combination of supercritical fluid and sonic energy
    Publication number: 20060065627
    Abstract: A method of processing a substrate. The method comprises flowing a supercritical fluid and a co-solvent across a substrate placed in a pressure tight vessel and applying a sonic energy to a surface of the substrate. The sonic energy can be an ultrasonic energy or a megasonic energy. The use of supercritical fluid and sonic energy can be used to clean a substrate, condition a surface of a substrate, to etch a substrate, to etch metal, to deliver materials to trenches and cavaties, and to selectively remove a polysilicon layer.
    Type: Application
    Filed: September 29, 2004
    Publication date: March 30, 2006
    Inventors: James Clarke, Kenneth Cadien, Justin Brask
  • Metal gate transistors with epitaxial source and drain regions
    Publication number: 20060068590
    Abstract: An MOS transistor formed on a heavily doped substrate is described. Metal gates are used in low temperature processing to prevent doping from the substrate from diffusing into the channel region of the transistor.
    Type: Application
    Filed: September 29, 2004
    Publication date: March 30, 2006
    Inventors: Nick Lindert, Justin Brask, Andrew Westmeyer
  • Metal gate electrode semiconductor device
    Publication number: 20060065939
    Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with NMOS and PMOS transistors that have high dielectric constant gate dielectric material over a semiconductor substrate. A metal barrier layer may be formed over the gate dielectric. A workfunction setting metal layer is formed over the metal barrier layer and a cap metal layer is formed over the workfunction setting metal layer.
    Type: Application
    Filed: September 27, 2004
    Publication date: March 30, 2006
    Inventors: Mark Doczy, Justin Brask, Jack Kavalieros, Chris Barns, Matthew Metz, Suman Datta, Robert Chau
  • Atomic layer deposition of high dielectric constant gate dielectrics
    Publication number: 20060060930
    Abstract: Gate dielectrics formed of silicates of hafnium or zirconium dioxide may be formed by atomic layer deposition. The precursors for the atomic layer deposition may include an oxidant, a silicate precursor, and a zirconium or hafnium precursor.
    Type: Application
    Filed: September 17, 2004
    Publication date: March 23, 2006
    Inventors: Matthew Metz, Clifford Boyd, Markus Kuhn, Suman Datta, Jack Kavalieros, Mark Doczy, Justin Brask, Robert Chau
  • Reducing ambipolar conduction in carbon nanotube transistors
    Publication number: 20060063318
    Abstract: Ambipolar conduction can be reduced in carbon nanotube transistors by forming a gate electrode of a metal. Metal sidewall spacers having different workfunctions than the gate electrode may be formed to bracket the metal gate electrode.
    Type: Application
    Filed: September 10, 2004
    Publication date: March 23, 2006
    Inventors: Suman Datta, Jack Kavalieros, Mark Doczy, Matthew Metz, Marko Radosavljevic, Amlan Majumdar, Justin Brask, Robert Chau
  • U-GATE TRANSISTORS AND METHODS OF FABRICATION
    Publication number: 20060063332
    Abstract: A process is described for manufacturing of non-planar multi-corner transistor structures. A fin of a semiconductor material having a mask on a top surface of the fin is formed on a first insulating layer. A second insulating layer is formed on the fin exposing a top surface of the mask, wherein a protection layer is deposited between the fin and the second insulating layer. Next, the mask is removed and spacers are formed on the fin adjacent to the protection layer. A recess having a bottom and opposing sidewalls is formed in the fin. A gate dielectric layer and a gate electrode are formed on the top surface, the opposing sidewalls of the fin and on the bottom and on the opposing sidewalls of the recess in the fin. A source region and a drain region are formed in the fin at the opposite sides of the gate electrode.
    Type: Application
    Filed: September 23, 2004
    Publication date: March 23, 2006
    Inventors: Brian Doyle, Surinder Singh, Uday Shah, Justin Brask, Robert Chau
  • Reducing oxidation under a high K gate dielectric
    Publication number: 20060057808
    Abstract: A metal layer is formed on a dielectric layer, which is formed on a substrate. After forming a masking layer on the metal layer, the exposed sides of the dielectric layer are covered with a polymer diffusion barrier.
    Type: Application
    Filed: September 10, 2004
    Publication date: March 16, 2006
    Inventors: Robert Turkot, Justin Brask, Jack Kavalieros, Mark Doczy, Matthew Metz, Uday Shah, Suman Datta, Robert Chau
  • Method for making a semiconductor device having a high-k gate dielectric
    Publication number: 20060051882
    Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.
    Type: Application
    Filed: August 22, 2005
    Publication date: March 9, 2006
    Inventors: Mark Doczy, Gilbert Dewey, Suman Datta, Sangwoo Pae, Justin Brask, Jack Kavalieros, Matthew Metz, Adrian Sherrill, Markus Kuhn, Robert Chau
  • Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
    Publication number: 20060051924
    Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part that is formed in the trench and a second part. After a first metal layer with a first workfunction is formed on the first and second parts of the second dielectric layer, part of the first metal layer is converted into a second metal layer with a second workfunction.
    Type: Application
    Filed: September 8, 2004
    Publication date: March 9, 2006
    Inventors: Mark Doczy, Justin Brask, Jack Kavalieros, Uday Shah, Matthew Metz, Suman Datta, Ramune Nagisetty, Robert Chau
  • Method for making a semiconductor device having a high-k gate dielectric
    Publication number: 20060051880
    Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.
    Type: Application
    Filed: September 7, 2004
    Publication date: March 9, 2006
    Inventors: Mark Doczy, Gilbert Dewey, Suman Datta, Sangwoo Pae, Justin Brask, Jack Kavalieros, Matthew Metz, Adrian Sherrill, Markus Kuhn, Robert Chau
  • Method for making a semiconductor device that includes a metal gate electrode
    Publication number: 20060051957
    Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer and a sacrificial structure that comprises a first layer and a second layer, such that the second layer is formed on the first layer and is wider than the first layer. After the sacrificial structure is removed to generate a trench, a metal gate electrode is formed within the trench.
    Type: Application
    Filed: September 7, 2004
    Publication date: March 9, 2006
    Inventors: Justin Brask, Jack Kavalieros, Mark Doczy, Matthew Metz, Suman Datta, Uday Shah, Brian Doyle, Robert Chau