Abstract: In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.

Abstract: A method for making a semiconductor device is described. That method comprises modifying a first surface, and forming a high-k gate dielectric layer on an unmodified second surface.

Abstract: A method for making a semiconductor device is described. That method comprises forming a sacrificial layer on a substrate, and forming a trench within the sacrificial layer. After forming a dummy gate electrode within the trench, a hard mask is formed on the dummy gate electrode and within the trench.

Abstract: A wafer may be rotated while etching to displace bubbles that may form, for example, from a reaction between silicon and water. As a result, a hydrophobic layer, which would otherwise be created by the bubbles, cannot form, resulting in a more uniform etch rate in some embodiments.

Abstract: Semiconductor integrated circuit structures, such as stacks containing metal layers, may be etched with a modified viscosity etchant. An increased viscosity etchant, for example, may reduce undercutting when a metal film is being etched.

Abstract: A method of patterning a thin film. The method includes forming a mask on a film to be patterned. The film is then etched in alignment with the mask to form a patterned film having a pair of laterally opposite sidewalls. A protective layer is formed on the pair of laterally opposite sidewalls. Next, the mask is removed from above the patterned film. After removing the mask from the patterned film, the protective layer is removed from the sidewalls.

Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a first gate dielectric layer that has a first substantially vertical component, then forming a first metal layer on the first gate dielectric layer. After forming on the substrate a second gate dielectric layer that has a second substantially vertical component, a second metal layer is formed on the second gate dielectric layer. In this method, a conductor is formed that contacts both the first metal layer and the second metal layer.

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and forming a masking layer on a first part of the high-k gate dielectric layer. After forming a first metal layer on the masking layer and on an exposed second part of the high-k gate dielectric layer, the masking layer is removed. A second metal layer is then formed on the first metal layer and on the first part of the high-k gate dielectric layer.

Abstract: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have vertical portions that may be exposed to a reduction reaction. As a result of the reduction reaction, the vertical portions may be converted to metal, which adds to the existing gate electrode. In some cases, removing the vertical dielectric portions reduces fringe capacitance and may also advantageously slightly increased underdiffusion without adding heat, in some embodiments.

Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.

Abstract: Capping of copper structures in hydrophobic interlayer dielectric layer, using aqueous electro-less bath is described herein.

Abstract: Semiconductor integrated circuit structures, such as stacks containing metal layers, may be etched with a modified viscosity etchant. An increased viscosity etchant, for example, may reduce undercutting when a metal film is being etched.

Abstract: The invention provides a strained silicon layer with a reduced roughness. Reduced cross-hatching in the strained silicon layer may allow the reduced roughness.

Abstract: A method for making a semiconductor device is described. That method comprises forming a polysilicon layer on a dielectric layer, which is formed on a substrate. The polysilicon layer is etched to generate a patterned polysilicon layer with an upper surface that is wider than its lower surface. The method may be applied, when using a replacement gate process to make transistors that have metal gate electrodes.

Abstract: Methods of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a gate dielectric layer, and then laser annealing the substrate.

Abstract: The present invention discloses a method including: providing a silicon wafer; forming a buried oxide (BOX) in the silicon wafer below a silicon body; and reducing a thickness of the silicon body by chemical thinning.

Abstract: A technique for reducing the number of silicon (Si) nano-crystals available to attach or otherwise deposit upon semiconductor device surfaces. More particularly, embodiments of the invention make a wafer substantially free of Si nano-crystals resulting from a wet etch of oxide layer portions, while not impairing semiconductor device dimensions or electrical characteristics.

Abstract: The mobility of carriers may be increased in strained channel epitaxial source/drain transistors. Doped silicon material may be blanket deposited after removing ion implanted source/drain regions. The blanket deposition forms amorphous films over non-source/drain areas and crystalline films in source/drain regions. By using an etch which is selective to amorphous silicon, the amorphous material may be removed. This may avoid some problems associated with selective deposition of the doped silicon material.

Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are uniformed in the semiconductor body on opposite sides of the gate electrode.

Abstract: A method of patterning a crystalline film. A crystalline film having a degenerate lattice comprising first atoms in a first region and a second region is provided. Dopants are substituted for said first atoms in said first region to form a non-degenerate crystalline film in said first region. The first region and the second region are exposed to a wet etchant wherein the wet etchant etches the degenerate lattice in said second region without etching the non-degenerate lattice in the first region.