Patents by Inventor Justin Gottschlich

Justin Gottschlich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190138423
    Abstract: An apparatus includes a data interface to obtain first sensor data from a first sensor and second sensor data from a second sensor of a monitored system; a data analyzer to extract a feature based on analyzing the first and second sensor data using a model, the model trained based on historical sensor data, the model to determine the feature as a deviation between the first and second sensor data to predict a future malfunction of the monitored system; an anomaly detector to detect an anomaly in at least one of the first sensor data or the second sensor data based on the feature, the anomaly corresponding to the future malfunction of the monitored system; and a system applicator to modify operation of the monitored system based on the anomaly.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Mats Agerstam, Bahareh Sadeghi, Jason Martin, Jeffrey Ota, Justin Gottschlich, Marcos Carranza, Maria Ramirez Loaiza, Alexander Heinecke, Mohammad Mejbah Ul Alam, Robert Colby, Sara Baghsorkhi, Shengtian Zhou
  • Publication number: 20190138719
    Abstract: Methods, apparatus, systems and articles of manufacture for detecting a side channel attack are disclosed. An example apparatus includes a histogram generator to generate a histogram representing cache access activities. A histogram analyzer is to determine at least one statistic based on the histogram. A machine learning model processor is to apply a machine learning model to the at least one statistic to attempt to identify a side channel attack. A multiple hypothesis tester to perform multiple hypothesis testing to determine a probability of the cache access activities being benign. An anomaly detection orchestrator is to, in response to the machine learning model processor identifying that the at least one statistic is indicative of the side channel attack and the probability not satisfying a similarity threshold, cause the performance of a responsive action to mitigate the side channel attack.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 9, 2019
    Inventors: Salmin Sultana, Li Chen, Abhishek Basak, Jason Martin, Justin Gottschlich
  • Publication number: 20190130762
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to validate data communicated by a vehicle. An example apparatus an anomaly detector to, in response to data communicated by a vehicle, at least one of compare an estimated speed with a reported speed or compare a location of the vehicle with a reported location. The apparatus including the anomaly detector further to generate an indication of the vehicle in response to the comparison. The apparatus further includes a notifier to discard data sent by the vehicle and notify surrounding vehicles of the data communicated by the vehicle.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 2, 2019
    Inventors: Liuyang Yang, Yair Yona, Moreno Ambrosin, Xiruo Liu, Hosein Nikopour, Shilpa Talwar, Kathiravetpillai Sivanesan, Sridhar Sharma, Debabani Choudhury, Kuilin Clark Chen, Jeffrey Ota, Justin Gottschlich
  • Publication number: 20190129822
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed. An example system includes a memory accessed by a program of interest, a performance monitoring unit to collect first memory access information and second memory access information about an object accessed in the memory by the program of interest; and a leak detector to: determine a non-access period based on the first memory access information and an unsupervised machine learning model trained based on the program of interest; and detect a potential memory leak of the program of interest based on the second memory access information and the non-access period.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 2, 2019
    Inventors: Mohammad Mejbah Ul Alam, Jason Martin, Justin Gottschlich, Alexander Heinecke, Shengtian Zhou
  • Publication number: 20190130101
    Abstract: Methods, apparatus, systems and articles of manufacture for detecting a side channel attack using hardware performance counters are disclosed. An example apparatus includes a hardware performance counter data organizer to collect a first value of a hardware performance counter at a first time and a second value of the hardware performance counter at a second time. A machine learning model processor is to apply a machine learning model to predict a third value corresponding to the second time. An error vector generator is to generate an error vector representing a difference between the second value and the third value. An error vector analyzer is to determine a probability of the error vector indicating an anomaly. An anomaly detection orchestrator is to, in response to the probability satisfying a threshold, cause the performance of a responsive action to mitigate the side channel anomaly.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 2, 2019
    Inventors: Li Chen, Abhishek Basak, Salmin Sultana, Justin Gottschlich
  • Patent number: 10191834
    Abstract: Methods and systems to identify and reproduce concurrency violations in multi-threaded programs are disclosed. An example method disclosed herein comprises determining whether a condition is met and serializing an operation of a first thread of a multi-threaded program relative to an operation of a second thread of the multi-threaded program. The serialization of the operations of the first and second threads results in a concurrency violation or bug thereby causing the multi-threaded program to crash. In this way, the operations of the first and second threads of the multi-threaded program that are responsible for the concurrency violation are identified and can be revised to remove the bug.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventors: Justin Gottschlich, Gilles Pokam, Cristiano Pereira, Jungwoo Ha
  • Publication number: 20170039070
    Abstract: A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads.
    Type: Application
    Filed: October 19, 2016
    Publication date: February 9, 2017
    Inventors: NATHAN D. DAUTENHAHN, JUSTIN GOTTSCHLICH, GILLES POKAM, CRISTIANO PEREIRA, SHILIANG HU, KLAUS DANNE, ROLF KASSA
  • Publication number: 20160224457
    Abstract: Methods and systems to identify and reproduce concurrency violations in multi-threaded programs are disclosed. An example method disclosed herein comprises determining whether a condition is met and serializing an operation of a first thread of a multi-threaded program relative to an operation of a second thread of the multi-threaded program. The serialization of the operations of the first and second threads results in a concurrency violation or bug thereby causing the multi-threaded program to crash. In this way, the operations of the first and second threads of the multi-threaded program that are responsible for the concurrency violation are identified and can be revised to remove the bug.
    Type: Application
    Filed: April 11, 2016
    Publication date: August 4, 2016
    Inventors: Justin Gottschlich, Gilles Pokam, Cristiano Pereira, Jungwoo Ha
  • Patent number: 9311143
    Abstract: Methods and systems to identify and reproduce concurrency violations in multi-threaded programs are disclosed. An example method disclosed herein comprises determining whether a condition is met and serializing an operation of a first thread of a multi-threaded program relative to an operation of a second thread of the multi-threaded program. The serialization of the operations of the first and second threads results in a concurrency violation or bug thereby causing the multi-threaded program to crash. In this way, the operations of the first and second threads of the multi-threaded program that are responsible for the concurrency violation are identified and can be revised to remove the bug.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: April 12, 2016
    Assignee: Intel Corporation
    Inventors: Justin Gottschlich, Gilles Pokam, Cristiano Pereira, Jungwoo Ha
  • Publication number: 20150363306
    Abstract: Methods and systems to identify threads responsible for causing a concurrency bug in a computer program having a plurality of concurrently executing threads are disclosed. An example method disclosed herein includes defining, with a processor, a data type. The data type including a first predicate, the first predicate being invoked using a first program instruction inserted in a first thread of the plurality of threads, a second predicate, the second predicate being invoked using a second program instruction inserted in a second thread of the plurality of threads, and an expression defining a relationship between the first predicate and the second predicate. The method further includes, in response to determining the relationship is satisfied during execution of the computer program, identifying the first thread and the second thread as responsible for the concurrency bug.
    Type: Application
    Filed: August 26, 2015
    Publication date: December 17, 2015
    Inventors: Youfeng Wu, Justin Gottschlich, Gilles Pokam, Shiliang Hu, Ali-Reza Adl-Tabatabai
  • Publication number: 20140115604
    Abstract: Methods and systems to identify and reproduce concurrency violations in multi-threaded programs are disclosed. An example method disclosed herein comprises determining whether a condition is met and serializing an operation of a first thread of a multi-threaded program relative to an operation of a second thread of the multi-threaded program. The serialization of the operations of the first and second threads results in a concurrency violation or bug thereby causing the multi-threaded program to crash. In this way, the operations of the first and second threads of the multi-threaded program that are responsible for the concurrency violation are identified and can be revised to remove the bug.
    Type: Application
    Filed: December 21, 2011
    Publication date: April 24, 2014
    Inventors: Justin Gottschlich, Gilles Pokam, Cristiano Pereira, Jungwoo Ha