Patents by Inventor Justin Gottschlich

Justin Gottschlich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11188643
    Abstract: Methods, apparatus, systems and articles of manufacture for detecting a side channel attack using hardware performance counters are disclosed. An example apparatus includes a hardware performance counter data organizer to collect a first value of a hardware performance counter at a first time and a second value of the hardware performance counter at a second time. A machine learning model processor is to apply a machine learning model to predict a third value corresponding to the second time. An error vector generator is to generate an error vector representing a difference between the second value and the third value. An error vector analyzer is to determine a probability of the error vector indicating an anomaly. An anomaly detection orchestrator is to, in response to the probability satisfying a threshold, cause the performance of a responsive action to mitigate the side channel anomaly.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: November 30, 2021
    Assignee: INTEL CORPORATION
    Inventors: Li Chen, Abhishek Basak, Salmin Sultana, Justin Gottschlich
  • Patent number: 11157384
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for code review assistance for dynamically typed languages. An example apparatus to analyze a segment of code includes a function identifier to identify a first input of a first function call included in the segment of the code, a parameter type vector (PTV) estimator model to estimate a first data structure based on the first input, the PTV estimator model generated via a set of reviewed code, a PTV determiner to generate a second data structure based on a data parameter type of the first input, an error comparator to determine a first reconstruction error based on the first data structure, and the second data structure and a recommendation generator to, if the first reconstruction error does not satisfy a recommendation threshold, generate a first recommendation to review the first function call.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: October 26, 2021
    Assignee: Intel Corporation
    Inventors: Marcos Carranza, Mats Agerstam, Justin Gottschlich, Alexander Heinecke, Cesar Martinez-Spessot, Maria Ramirez Loaiza, Mohammad Mejbah Ul Alam, Shengtian Zhou
  • Publication number: 20210304613
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to validate data communicated by a vehicle. An example apparatus an anomaly detector to, in response to data communicated by a vehicle, at least one of compare an estimated speed with a reported speed or compare a location of the vehicle with a reported location. The apparatus including the anomaly detector further to generate an indication of the vehicle in response to the comparison. The apparatus further includes a notifier to discard data sent by the vehicle and notify surrounding vehicles of the data communicated by the vehicle.
    Type: Application
    Filed: April 9, 2021
    Publication date: September 30, 2021
    Inventors: Liuyang Yang, Yair Yona, Moreno Ambrosin, Xiruo Liu, Hosein Nikopour, Shilpa Talwar, Kathiravetpillai Sivanesan, Sridhar Sharma, Debabani Choudhury, Kuilin Clark Chen, Jeffrey Ota, Justin Gottschlich
  • Patent number: 11074344
    Abstract: Methods, apparatus, systems and articles of manufacture to identify a side-channel attack are disclosed. An example apparatus includes a vector-to-neuron processor to map an event vector to a neuron of a trained self-organizing map; a buffer processor to identify a task pair based on the neuron and an adjacent neuron of the neuron; a buffer to store data corresponding to the identified task pair; an attack identifier to, when information stored in the buffer corresponds to more than a threshold number of task pairs corresponding to the identified task pair, identify a malware attack; and a mitigation technique selector to select a technique for mitigating the malware attack.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 27, 2021
    Assignee: Intel Corporation
    Inventors: Mohammad Mejbah Ul Alam, Justin Gottschlich, Shengtian Zhou
  • Patent number: 11061650
    Abstract: Methods and apparatus to automatically generate code for graphical user interfaces are disclosed. An example apparatus includes a textual description analyzer to encode a user-provided textual description of a GUI design using a first neural network. The example apparatus further includes a DSL statement generator to generate a DSL statement with a second neural network. The DSL statement is to define a visual element of the GUI design. The DSL statement is generated based on at least one of the encoded textual description or a user-provided image representative of the GUI design. The example apparatus further includes a rendering tool to render a mockup of the GUI design based on the DSL statement.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Javier Sebastian Turek, Javier Felip Leon, Luis Carlos Maria Remis, David Israel Gonzalez Aguirre, Ignacio Javier Alvarez, Justin Gottschlich
  • Publication number: 20210182031
    Abstract: Methods, systems, and apparatus for automatic detection of software bugs are disclosed. An example apparatus includes a comparator to compare reference code to input code to detect a source code error in the input code; a graph generator to generate a graphical representation of the reference code or the input code, the graphical representation to identify non-overlapping code regions; and a root cause determiner to determine a root cause of the source code error in the input code, the root cause based on the non-overlapping code regions.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 17, 2021
    Inventors: Fangke Ye, Justin Gottschlich, Shengtian Zhou, Roshni Iyer, Jesmin Jahan Tithi
  • Patent number: 11036477
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed improve utilization of a heterogeneous system executing software. The disclosed methods, apparatus, systems and articles of manufacture include an apparatus comprising a variant manager to determine whether an algorithm is a candidate for sub-algorithmic partitioning (SAP) based on at least one of a first size of input data to the algorithm and a second size of output data from the algorithm; a partitioner to partition the algorithm into at least a first tile and a second tile; and a compiler to compile a first variant based on the first tile and a second variant based on the second tile into an executable file, the first variant to be executed on a first processing element of the heterogeneous system, the second variant to be executed on a second processing element of the heterogeneous system.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 15, 2021
    Assignee: INTEL CORPORATION
    Inventors: Adam Herr, Sridhar Sharma, Mikael Bourges-Sevenier, Justin Gottschlich
  • Patent number: 11024180
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to validate data communicated by a vehicle. An example apparatus an anomaly detector to, in response to data communicated by a vehicle, at least one of compare an estimated speed with a reported speed or compare a location of the vehicle with a reported location. The apparatus including the anomaly detector further to generate an indication of the vehicle in response to the comparison. The apparatus further includes a notifier to discard data sent by the vehicle and notify surrounding vehicles of the data communicated by the vehicle.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Liuyang Yang, Yair Yona, Moreno Ambrosin, Xiruo Liu, Hosein Nikopour, Shilpa Talwar, Kathiravetpillai Sivanesan, Sridhar Sharma, Debabani Choudhury, Kuilin Clark Chen, Jeffrey Ota, Justin Gottschlich
  • Publication number: 20210157968
    Abstract: Systems and methods for determining a configuration for a microarchitecture are described herein. An example system includes a proposal generator to generate a first candidate configuration of parameters for the microarchitecture, a machine learning model to process the first candidate configuration of parameters to output estimated performance indicators for the microarchitecture, an uncertainty checker to determine whether the estimated performance indicators are reliable, and a performance checker. In response to a determination that the estimated performance indicators are reliable, the performance checker is to determine whether the estimated performance indicators have improved toward a target. Further, if the estimated performance indicators have improved, the performance checker is to store the first candidate configuration of parameters in a memory as a potential solution for a microarchitecture without performing a full simulation on the first candidate configuration of parameters.
    Type: Application
    Filed: November 30, 2020
    Publication date: May 27, 2021
    Inventors: Javier Sebastián Turek, Javier Felip Leon, Alexander Heinecke, Evangelos Georganas, Luis Carlos Maria Remis, Ignacio Javier Alvarez, David Israel Gonzalez Aguirre, Shengtian Zhou, Justin Gottschlich
  • Patent number: 11003444
    Abstract: An apparatus includes a software parser to generate a plurality of abstract syntax trees based on a plurality of software files, the ASTs including subtrees corresponding to a plurality of functions of the software files, a subtree encoder to generate a plurality of code vectors representative of one or more semantic properties of the subtrees, a function identifier to determine a plurality of clusters for the subtrees and assign a cluster identifier and a function label to the subtrees, a tree database to store the subtrees and map the plurality of subtrees to respective ones of cluster identifiers and function names, and a processor to: train a model based on a feature vector and the plurality of clusters stored in the tree database and predict the cluster identifier for the subtrees, based on the trained model, to identify a name of the function.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Shengtian Zhou, Mohammad Mejbah ul Alam, Justin Gottschlich
  • Publication number: 20210117807
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to construct and compare program-derived semantic graphs comprising a leaf node creator to identify a first set of nodes within a parse tree, set a first abstraction level of a program-derived semantic graph (PSG) to contain the first set of nodes, an abstraction level determiner to access a second set of nodes, the second set of nodes to include the set of nodes in the PSG, create a third set of nodes, the third set of nodes to include the set of possible nodes at an abstraction level, determine whether the abstraction level is deterministic, a rule-based abstraction level creator to in response to determining the abstraction level is deterministic, construct the abstraction level, and a PSG comparator to access a first PSG and a second PSG, determine if the first PSG and the second PSG satisfy a similarity threshold.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 22, 2021
    Inventors: Shengtian Zhou, Fangke Ye, Roshni G. Iyer, Jesmin Jahan Tithi, Justin Gottschlich
  • Publication number: 20210110308
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for finding optimization opportunities in machine-readable instructions, the apparatus comprising, a cluster creator to utilize a semantic similarity model to create a first cluster of semantically similar machine-readable instruction snippets selected from a set of machine-readable instructions, a combination generator to identify a first combination of a subset of the semantically similar machine-readable instruction snippets from the first cluster of semantically similar machine-readable instruction snippets, and a snippet analyzer to utilize a syntactic similarity model to determine a syntactic similarity of the first combination of a subset of the semantically similar machine-readable instruction snippets from the first cluster of semantically similar machine-readable instruction snippets.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Inventor: Justin Gottschlich
  • Publication number: 20210103434
    Abstract: An example apparatus comprises a transformation generator to generate a population of code variants corresponding to an input code, the population of code variants to include transformation sequences of the input code, a dependence analyzer to analyze the population of code variants for dependence vectors, a profile controller to profile the population of code variants to determine performance metrics of hardware during an execution of respective ones of the transformation sequences, and a hash code generator to generate hash codes for storing in a database, the hash codes (a) corresponding to a combination of the dependence vectors and respective performance metrics and (b) mapped to respective transformation sequences.
    Type: Application
    Filed: November 24, 2020
    Publication date: April 8, 2021
    Inventors: Anand Venkat, Justin Gottschlich, Shengtian Zhou, Vasileios Porpodas
  • Patent number: 10956298
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed. An example system includes a memory accessed by a program of interest, a performance monitoring unit to collect first memory access information and second memory access information about an object accessed in the memory by the program of interest; and a leak detector to: determine a non-access period based on the first memory access information and an unsupervised machine learning model trained based on the program of interest; and detect a potential memory leak of the program of interest based on the second memory access information and the non-access period.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: March 23, 2021
    Assignee: INTEL CORPORATION
    Inventors: Mohammad Mejbah Ul Alam, Jason Martin, Justin Gottschlich, Alexander Heinecke, Shengtian Zhou
  • Publication number: 20210081310
    Abstract: Methods, apparatus, systems and articles of manufacture for self-supervised software defect detection are disclosed. An example apparatus includes a control structure miner to identify a plurality of code snippets in an instruction repository, the code snippets to represent control structures, the control structure miner to identify types of control structures of the code snippets; a cluster generator to generate a plurality of clusters of code snippets, respective ones of the clusters of the code snippets corresponding to different types of control structures; and a snippet ranker to label at least one code snippet of corresponding ones of the clusters of the code snippets as at least one reference code snippet, the at least one reference code snippets to be compared against a test code snippet to detect the defect in the software.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Inventor: Justin Gottschlich
  • Publication number: 20210073632
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for generating code semantics. An example apparatus includes a concept controller to assign semantic labels to repository data to generate a training set, the semantic labels stored in a first semantic graph, the training set including a first code block associated with a first semantic label and a second code block associated with a second semantic label, a concept determiner to generate a first block embedding based on the first code block and a second block embedding based on the second code block, a graph generator to link the first block embedding to the second block embedding to form a second semantic graph, and a graph parser to output at least one of the first code block or the second code block corresponding to a query based on the second semantic graph.
    Type: Application
    Filed: November 18, 2020
    Publication date: March 11, 2021
    Inventors: Roshni G. Iyer, Justin Gottschlich, Joseph Tarango, Jim Baca, Niranjan Hasabnis
  • Publication number: 20210073391
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve security of computer programs using code abstraction. An example method includes parsing a first representation of an algorithm in a base language for an operator associated with the base language; based on the operator, identifying a vulnerability in the first representation of the algorithm; identifying a target language to represent the algorithm; and converting the first representation of the algorithm in the base language to a second representation of the algorithm in the target language to remediate the vulnerability.
    Type: Application
    Filed: November 13, 2020
    Publication date: March 11, 2021
    Inventor: Justin Gottschlich
  • Patent number: 10908884
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for runtime scheduling of software executing on a heterogeneous system. An example apparatus includes in response to a variant compiler to generate a representation of an algorithm in a domain-specific language (DSL), a compilation auto-scheduler to generate a schedule based on configurations for processing elements of the heterogeneous system, the processing elements including at least a first and a second processing element, the variant compiler to compile variant binaries based on the schedule, each of the variant binaries associated with the algorithm in the DSL, the variant binaries including a first variant binary corresponding to the first processing element and a second variant binary corresponding to the second processing element, and an application compiler to generate a fat binary including a runtime scheduler to select one or more of the variant binaries to execute a workload based on the schedule.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: February 2, 2021
    Assignee: INTEL CORPORATION
    Inventors: Adam Herr, Derek Gerstmann, Justin Gottschlich, Mikael Bourges-Sevenier, Sridhar Sharma
  • Patent number: 10853554
    Abstract: Systems and methods for determining a configuration for a microarchitecture are described herein. An example system includes a proposal generator to generate a first candidate configuration of parameters for the microarchitecture, a machine learning model to process the first candidate configuration of parameters to output estimated performance indicators for the microarchitecture, an uncertainty checker to determine whether the estimated performance indicators are reliable, and a performance checker. In response to a determination that the estimated performance indicators are reliable, the performance checker is to determine whether the estimated performance indicators have improved toward a target. Further, if the estimated performance indicators have improved, the performance checker is to store the first candidate configuration of parameters in a memory as a potential solution for a microarchitecture without performing a full simulation on the first candidate configuration of parameters.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Javier Sebastian Turek, Javier Felip Leon, Alexander Heinecke, Evangelos Georganas, Luis Carlos Maria Remis, Ignacio Javier Alvarez, David Israel Gonzalez Aguirre, Shengtian Zhou, Justin Gottschlich
  • Patent number: 10802942
    Abstract: An apparatus includes a data interface to obtain first sensor data from a first sensor and second sensor data from a second sensor of a monitored system; a data analyzer to extract a feature based on analyzing the first and second sensor data using a model, the model trained based on historical sensor data, the model to determine the feature as a deviation between the first and second sensor data to predict a future malfunction of the monitored system; an anomaly detector to detect an anomaly in at least one of the first sensor data or the second sensor data based on the feature, the anomaly corresponding to the future malfunction of the monitored system; and a system applicator to modify operation of the monitored system based on the anomaly.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Mats Agerstam, Bahareh Sadeghi, Jason Martin, Jeffrey Ota, Justin Gottschlich, Marcos Carranza, Maria Ramirez Loaiza, Alexander Heinecke, Mohammad Mejbah Ul Alam, Robert Colby, Sara Baghsorkhi, Shengtian Zhou