Patents by Inventor Justin J. Song
Justin J. Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11435809Abstract: A system with improved power performance for tasks executed in parallel. A plurality of processing cores each to execute tasks. An inter-core messaging unit to conveys messages between the cores. A power management agent transitions a first core into a lower power state responsive to the first core waiting for a second core to complete a second task. In some embodiments long messages are subdivided to allow a receiving core to resume useful work sooner.Type: GrantFiled: May 3, 2021Date of Patent: September 6, 2022Assignee: Intel CorporationInventors: Devadatta V. Bodas, Muralidhar Rajappa, Justin J. Song, Andy Hoffman
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Publication number: 20210365096Abstract: A system with improved power performance for tasks executed in parallel. A plurality of processing cores each to execute tasks. An inter-core messaging unit to conveys messages between the cores. A power management agent transitions a first core into a lower power state responsive to the first core waiting for a second core to complete a second task. In some embodiments long messages are subdivided to allow a receiving core to resume useful work sooner.Type: ApplicationFiled: May 3, 2021Publication date: November 25, 2021Applicant: Intel CorporationInventors: Devadatta V. Bodas, Muralidhar Rajappa, Justin J. Song, Andy Hoffman
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Patent number: 10996737Abstract: A system with improved power performance for tasks executed in parallel. A plurality of processing cores each to execute tasks. An inter-core messaging unit to conveys messages between the cores. A power management agent transitions a first core into a lower power state responsive to the first core waiting for a second core to complete a second task. In some embodiments long messages are subdivided to allow a receiving core to resume useful work sooner.Type: GrantFiled: March 31, 2016Date of Patent: May 4, 2021Assignee: Intel CorporationInventors: Devadatta V. Bodas, Muralidhar Rajappa, Justin J. Song, Andy Hoffman
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Patent number: 10963031Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.Type: GrantFiled: February 27, 2018Date of Patent: March 30, 2021Assignee: Intel CorporationInventors: Brian J. Griffith, Viktor D. Vogman, Justin J. Song
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Patent number: 10904127Abstract: A zombie server can be detected. Detecting a zombie server can include labeling a plurality of processes as utility software, calculating a utilization of utility software on the plurality of processes executed in one or more processing resources during an interval of time, and calculating a server utilization of the one or more processing resources during the interval of time. Detecting the zombie server can also include determining whether a difference between the utilization of utility software and the server utilization is greater than a threshold, and identifying a server that hosts the processing resource as a zombie server based on a determination that the difference is smaller than the threshold.Type: GrantFiled: June 13, 2016Date of Patent: January 26, 2021Assignee: Intel CorporationInventors: Devadatta Bodas, Justin J. Song, Muralidhar Rajappa, Andy Hoffman
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Patent number: 10719107Abstract: A method and apparatus for node power regulation among nodes that share a power supply are described. In one embodiment, the apparatus comprises a power supply unit to provide input power and a plurality of nodes coupled to receive the input power, where each node of the plurality of nodes is operable to run power management logic, and wherein two or more nodes of the plurality of nodes alternate between performing power management and providing power regulation control information to other nodes of the plurality of nodes to regulate power consumption by the plurality of nodes, with, at any one time, only one node of plurality of nodes generating the power regulation control to regulate power for the plurality of nodes.Type: GrantFiled: March 29, 2016Date of Patent: July 21, 2020Assignee: INTEL CORPORATIONInventors: Justin J. Song, Devadatta V. Bodas, Muralidhar Rajappa, Brian J. Griffith, Andy Hoffman, Gopal R. Mundada
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Patent number: 10644963Abstract: A zombie server can be detected. Detecting a zombie server can include receiving, at a server, network traffic and calculating a percentage of the network traffic as being productivity software layer 7 protocols every first time interval. Detecting a zombie server can also include marking the server as a zombie server based on the percentage every second time interval and processing the network traffic at the server to perform a number of actions by the productivity software.Type: GrantFiled: June 13, 2016Date of Patent: May 5, 2020Assignee: Intel CorporationInventors: Devadatta Bodas, Justin J. Song, Muralidhar Rajappa, Andy Hoffman
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Patent number: 10404676Abstract: A method and apparatus for coordinating and authenticating requests for data. In one embodiment, the apparatus comprises: a baseboard management controller (BMC); and a request coordinator coupled to the BMC to intercept BMC requests and to provide intercepted requests to the BMC, where the coordination interface comprises a request parser to parse parameters for each of the BMC requests, one or more queues to store the requests while the BMC is servicing another BMC request, and a command submitter to send individual BMC requests to the BMC, wherein the BMC is operable to generate the responses to the BMC requests received from the coordination interface and to send the responses to the coordination interface.Type: GrantFiled: March 29, 2016Date of Patent: September 3, 2019Assignee: INTEL CORPORATIONInventors: Justin J. Song, Devadatta V. Bodas, Muralidhar Rajappa, Andy Hoffman, Mariusz Oriol, Gopal R. Mundada
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Patent number: 10261559Abstract: In one embodiment, the present invention includes a method for providing power state change information from a plurality of cores of a processor to a predictor at a periodic interval and generating a prediction to indicate a predicted operation level of the cores during a next operating period. Other embodiments are described and claimed.Type: GrantFiled: February 10, 2016Date of Patent: April 16, 2019Assignee: Intel CorporationInventors: Justin J. Song, Qian Diao
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Publication number: 20180188790Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.Type: ApplicationFiled: February 27, 2018Publication date: July 5, 2018Applicant: INTEL CORPORATIONInventors: Brian J. Griffith, Viktor D. Vogman, Justin J. Song
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Patent number: 9971391Abstract: A method of assessing energy efficiency of a High-performance computing (HPC) system, including: selecting a plurality of HPC workloads to run on a system under test (SUT) with one or more power constraints, wherein the SUT includes a plurality of HPC nodes in the HPC system, executing the plurality of HPC workloads on the SUT, and generating a benchmark metric for the SUT based on a baseline configuration for each selected HPC workload and a plurality of measured performance per power values for each executed workload at each selected power constraint is shown.Type: GrantFiled: December 23, 2015Date of Patent: May 15, 2018Assignee: Intel CorporationInventors: Devadatta Bodas, Meenakshi Arunachalam, Ilya Sharapov, Charles R. Yount, Scott B. Huck, Ramakrishna Huggahalli, Justin J. Song, Brian J. Griffith, Muralidhar Rajappa, Lingdan (Linda) Zeng
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Patent number: 9939834Abstract: A system and method for computing at a facility having systems of multiple compute nodes to execute jobs of computing. Power consumption of the facility is managed to within a power band. The power consumption may be adjusted by implementing (e.g., by a power balloon) activities having little or no computational output.Type: GrantFiled: December 24, 2014Date of Patent: April 10, 2018Assignee: Intel CorporationInventors: Devadatta V. Bodas, Muralidhar Rajappa, Justin J. Song, Andy Hoffman, Michael K. Patterson
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Patent number: 9933829Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.Type: GrantFiled: September 7, 2016Date of Patent: April 3, 2018Assignee: INTEL CORPORATIONInventors: Brian J. Griffith, Viktor D. Vogman, Justin J. Song
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Patent number: 9927857Abstract: A process identifier for a job is collected. The job runs on a plurality of nodes. The job is identified using the process identifier. A node for the job is identified. An amount of power consumed by the node to run the job is determined.Type: GrantFiled: December 24, 2014Date of Patent: March 27, 2018Assignee: INTEL CORPORATIONInventors: Justin J. Song, Devadatta V. (Deva) Bodas, Muralidhar (Murali) Rajappa, Andy Hoffman, James W. (Jimbo) Alexander, Joseph A. Schaefer, Sunil K. Mahawar
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Patent number: 9921633Abstract: An indication of a mode for a job is received. An available power for the job is determined based on the mode. A first power for the job is allocated based on the available power. A first frequency for the job is determined based on the available power. The first power is adjusted based on the available power.Type: GrantFiled: December 24, 2014Date of Patent: March 20, 2018Assignee: INTEL CORPORATIONInventors: Devadatta V. (Deva) Bodas, Justin J. Song, Muralidhar (Murali) Rajappa, Andy Hoffman, James W. (Jimbo) Alexander, Joseph A. Schaefer, Sunil K. Mahawar
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Patent number: 9851771Abstract: Dynamic monitoring of current draw by a memory device or memory subsystem can enable a power management system to adjust a memory access performance parameter based on monitored power usage. The system can generate a power usage characterization for the memory device and/or memory subsystem based on monitoring current draw for a known pattern, and then subsequently use the power usage characterization to determine how to adjust the memory access performance parameter.Type: GrantFiled: December 28, 2013Date of Patent: December 26, 2017Assignee: Intel CorporationInventors: Lawrence A Cooper, Justin J Song, Xiuting C Man, Nagi Aboulenein, Christopher E Cox, Rebecca Z Loop
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Publication number: 20170359246Abstract: A zombie server can be detected. Detecting a zombie server can include labeling a plurality of processes as utility software, calculating a utilization of utility software on the plurality of processes executed in one or more processing resources during an interval of time, and calculating a server utilization of the one or more processing resources during the interval of time. Detecting the zombie server can also include determining whether a difference between the utilization of utility software and the server utilization is greater than a threshold, and identifying a server that hosts the processing resource as a zombie server based on a determination that the difference is smaller than the threshold.Type: ApplicationFiled: June 13, 2016Publication date: December 14, 2017Applicant: INTEL CORPORATIONInventors: Devadatta Bodas, Justin J. Song, Muralidhar Rajappa, Andy Hoffman
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Publication number: 20170359226Abstract: A zombie server can be detected. Detecting a zombie server can include receiving, at a server, network traffic and calculating a percentage of the network traffic as being productivity software layer 7 protocols every first time interval. Detecting a zombie server can also include marking the server as a zombie server based on the percentage every second time interval and processing the network traffic at the server to perform a number of actions by the productivity software.Type: ApplicationFiled: June 13, 2016Publication date: December 14, 2017Applicant: INTEL CORPORATIONInventors: Devadatta Bodas, Justin J. Song, Muralidhar Rajappa, Andy Hoffman
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Publication number: 20170285717Abstract: A system with improved power performance for task executed in parallel. A plurality of processing cores each to execute tasks. An inter-core messaging unit to conveys messages between the cores. A power management agent transitions a first core into a lower power state responsive to the first core waiting for a second core to complete a second task. In some embodiments long messages are subdivided to allow a receiving core to resume useful work sooner.Type: ApplicationFiled: March 31, 2016Publication date: October 5, 2017Inventors: DEVADATTA V. BODAS, MURALIDHAR RAJAPPA, JUSTIN J. SONG, ANDY HOFFMAN
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Publication number: 20170285702Abstract: A method and apparatus for node power regulation among nodes that share a power supply are described. In one embodiment, the apparatus comprises a power supply unit to provide input power and a plurality of nodes coupled to receive the input power, where each node of the plurality of nodes is operable to run power management logic, and wherein two or more nodes of the plurality of nodes alternate between performing power management and providing power regulation control information to other nodes of the plurality of nodes to regulate power consumption by the plurality of nodes, with, at any one time, only one node of plurality of nodes generating the power regulation control to regulate power for the plurality of nodes.Type: ApplicationFiled: March 29, 2016Publication date: October 5, 2017Inventors: Justin J. Song, Devadatta V. Bodas, Muralidhar Rajappa, Brian J. Griffith, Andy Hoffman, Gopal R. Mundada