Abstract: A method and apparatus for coordinating and authenticating requests for data. In one embodiment, the apparatus comprises: a baseboard management controller (BMC); and a request coordinator coupled to the BMC to intercept BMC requests and to provide intercepted requests to the BMC, where the coordination interface comprises a request parser to parse parameters for each of the BMC requests, one or more queues to store the requests while the BMC is servicing another BMC request, and a command submitter to send individual BMC requests to the BMC, wherein the BMC is operable to generate the responses to the BMC requests received from the coordination interface and to send the responses to the coordination interface.

Abstract: A method of assessing energy efficiency of a High-performance computing (HPC) system, including: selecting a plurality of HPC workloads to run on a system under test (SUT) with one or more power constraints, wherein the SUT includes a plurality of HPC nodes in the HPC system, executing the plurality of HPC workloads on the SUT, and generating a benchmark metric for the SUT based on a baseline configuration for each selected HPC workload and a plurality of measured performance per power values for each executed workload at each selected power constraint is shown.

Abstract: A system and method for distributed computing, including executing a job of distributed computing on compute nodes. The speed of parallel tasks of the job executing on the compute nodes are adjusted to increase performance of the job or to lower power consumption of the job, or both, wherein the adjusting is based on imbalances of respective speeds of the parallel tasks.

Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.

Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.

Abstract: In one embodiment, the present invention includes a method for providing power state change information from a plurality of cores of a processor to a predictor at a periodic interval and generating a prediction to indicate a predicted operation level of the cores during a next operating period. Other embodiments are described and claimed.

Abstract: A system and method for distributed computing, including executing a job of distributed computing on compute nodes. The speed of parallel tasks of the job executing on the compute nodes are adjusted to increase performance of the job or to lower power consumption of the job, or both, wherein the adjusting is based on imbalances of respective speeds of the parallel tasks.

Abstract: A system and method for computing including compute units to execute a computing event, the computing event being a server application or a distributed computing job. A power characteristic or a thermal characteristic, or a combination thereof, of the compute units is determine. One or more of the compute units is selected to execute the computing event based on a selection criterion and on the characteristic.

Abstract: A system and method for forecasting power consumption at a facility, the facility having a system of compute units for executing jobs of computing. The forecast of power includes forecasting sequence of jobs execution on a system of the nodes over time, estimating power for the jobs of the system, and developing a system-level power forecast.

Abstract: A system and method for computing at a facility having systems of multiple compute nodes to execute jobs of computing. Power consumption of the facility is managed to within a power band. The power consumption may be adjusted by implementing (e.g., by a power balloon) activities having little or no computational output.

Abstract: An indication of a mode for a job is received. An available power for the job is determined based on the mode. A first power for the job is allocated based on the available power. A first frequency for the job is determined based on the available power. The first power is adjusted based on the available power.

Abstract: A process identifier for a job is collected. The job runs on a plurality of nodes. The job is identified using the process identifier. A node for the job is identified. An amount of power consumed by the node to run the job is determined.

Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.

Abstract: Dynamic monitoring of current draw by a memory device or memory subsystem can enable a power management system to adjust a memory access performance parameter based on monitored power usage. The system can generate a power usage characterization for the memory device and/or memory subsystem based on monitoring current draw for a known pattern, and then subsequently use the power usage characterization to determine how to adjust the memory access performance parameter.

Abstract: On a multi-core processor that supports simultaneous multi-threading, the power state for each logical processor is tracked. Upon indication that a logical processor is ready to transition into a deep low power state, software remapping (e.g., thread-hopping) may be performed. Accordingly, if multiple logical processors, on different cores, are in a low-power state, they are re-mapped to same core and the core is then placed into a low power state. Other embodiments are described and claimed.

Abstract: On a multi-core processor that supports simultaneous multi-threading, the power state for each logical processor is tracked. Upon indication that a logical processor is ready to transition into a deep low power state, software remapping (e.g., thread-hopping) may be performed. Accordingly, if multiple logical processors, on different cores, are in a low-power state, they are re-mapped to same core and the core is then placed into a low power state. Other embodiments are described and claimed.

Abstract: An apparatus and method is described herein for avoiding inefficient core hopping and providing hardware assisted power state selection. Future idle-activity of cores is predicted. If the residency of activity patterns for efficient core hop scenarios is predicted to be large enough, a core is determined to be efficient and allowed. However, if efficient activity patterns are not predicted to be resident for long enough—inefficient patterns are instead predicted to be resident for longer—then a core hop request is denied. As a result, designers may implement a policy for avoiding core hops that weighs the potential gain of the core hop, such as alleviation of a core hop condition, against a penalty for performing the core hop, such as a temporal penalty for the core hop. Separately, idle durations associated with hardware power states for cores may be predicted in hardware. Furthermore, accuracy of the idle duration prediction is determined.

Abstract: In some embodiments, the invention involves modification of the processor utilization calculations that are used by operating system power management services to improve processor efficiency. An embodiment of the present invention is a system and method relating to power management policies under operating system control. In at least one embodiment, the present invention is intended to modify the processor utilization evaluation process so that C-state transition time and/or unhalted reference cycles are included in the calculation. Other embodiments are described and claimed.

Abstract: An apparatus and method is described herein for avoiding inefficient core hopping and providing hardware assisted power state selection. Future idle-activity of cores is predicted. If the residency of activity patterns for efficient core hop scenarios is predicted to be large enough, a core is determined to be efficient and allowed. However, if efficient activity patterns are not predicted to be resident for long enough—inefficient patterns are instead predicted to be resident for longer—then a core hop request is denied. As a result, designers may implement a policy for avoiding core hops that weighs the potential gain of the core hop, such as alleviation of a core hop condition, against a penalty for performing the core hop, such as a temporal penalty for the core hop. Separately, idle durations associated with hardware power states for cores may be predicted in hardware. Furthermore, accuracy of the idle duration prediction is determined.

Abstract: In some embodiments, the invention involves modification of the processor utilization calculations that are used by operating system power management services to improve processor efficiency. An embodiment of the present invention is a system and method relating to power management policies under operating system control. In at least one embodiment, the present invention is intended to modify the processor utilization evaluation process so that C-state transition time and/or unhalted reference cycles are included in the calculation. Other embodiments are described and claimed.