Abstract: Mapping computers and ports of power distribution units in a data center, the data center including a plurality of computers and a data center management server, each computer in the data center connected for power to one of a plurality of power distribution unit (‘PDU’) ports of a PDU, each PDU connected through the communications module and a data communications network to the data center management server, including generating, by a power modulating module of a computer, a power consumption signal in the PDU, the power consumption signal encoding a unique identification of the computer; demodulating, by the PDU, the power consumption signal, including retrieving from the signal the unique identification of the computer; and reporting, by the PDU to the data center management server, an association of the unique identification of the computer and a PDU port.

Abstract: Methods, apparatus, and products for detecting an increase in thermal resistance of a heat sink in a computer system, the heat sink dissipating heat for a component of the computer system, the computer system including a fan controlling airflow across the heat sink, the computer system also including a temperature monitoring device, including: measuring, by a monitoring module through use of the temperature monitoring device during operation of the computer system, thermal resistance of the heat sink; determining whether the measured thermal resistance of the heat sink is greater than a threshold thermal resistance, the threshold thermal resistance stored in a thermal profile in non-volatile memory, and if the measured thermal resistance of the heat sink is greater than the threshold thermal resistance, notifying a system administrator.

Abstract: Methods, apparatus, and products are disclosed for optimizing a physical data communications topology between a plurality of computing nodes, the physical data communications topology including physical links configured to connect the plurality of nodes for data communications, that include carrying out repeatedly at a predetermined pace: detecting network packets transmitted through the links between each pair of nodes in the physical data communications topology, each network packet characterized by one or more packet attributes; assigning, to each network packet, a packet weight in dependence upon the packet attributes for that network packet; determining, for each pair of nodes in the physical data communications topology, a node pair traffic weight in dependence upon the packet weights assigned to the network packets transferred between that pair of nodes; and reconfiguring the physical links between each pair of nodes in dependence upon the node pair traffic weights.

Abstract: Methods and systems are disclosed for providing independent clock failover for scalable blade servers that include assigning a server blade to one of a plurality of clock failover groups, providing a plurality of independent clock signals to the clock generator of the server blade, wherein one of the plurality of independent clock signals is an active clock signal, detecting a failover condition for the clock failover group assigned to the server blade, and switching the active clock signal, in response to the detected failover condition, from one independent clock signal to another independent clock signal.

Abstract: Computer memory subsystems are disclosed for enhancing signal quality that include: one or more memory modules; a memory bus; and a memory controller connected to the memory modules through the memory bus, the memory controller including a reception buffer connected to the memory bus, the reception buffer capable of receiving an input signal from one of the memory modules, the memory controller including a reception characteristics table capable of storing reception characteristics for each of the memory modules connected to the memory controller, the memory controller including an equalizer connected to the reception buffer and the reception characteristics table, the equalizer capable of equalizing the received input signal in dependence upon the reception characteristics for the memory module from which the input signal was received, and the memory controller including memory controller logic connected to the equalizer, the memory controller logic capable of processing the equalized input signal.

Abstract: The invention is directed to providing a virtualized blade flash with a management module in a blade server. A method of configuring a blade server according to an embodiment of the invention includes: providing a plurality of blades, wherein each blade comprising: a service processor; a chip set; an at least one central processing unit (CPU); providing a management module in communication with each of the plurality of blades; and adding a virtual flash store at the management module.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory switching data processing system is provided. The memory switching data processing system includes one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules.

Abstract: A memory switching data processing system including one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules.

Abstract: Establishing, with a USB RAID controller connected to a USB hub and with USB mass storage devices connected to the USB hub and the USB RAID controller through USB connectors, the USB hub controlled by a USB host controller, a RAID array including enumerating, by the USB host controller, the USB mass storage devices, including discovering the USB RAID controller; receiving, by the USB RAID controller from a RAID console application program, an instruction to designate USB connectors as RAIDable USB connectors, the instruction including selected USB connectors; designating, by the USB RAID controller, the selected USB connectors as RAIDable USB connectors; enumerating by the USB RAID controller the USB mass storage devices connected to the RAIDable USB connectors; configuring by the USB RAID controller a RAID array, the RAID array including the USB mass storage devices; and storing, through the USB RAID controller, computer data on the RAID array.

Abstract: A method of transmitting a signal on a bi-directional universal serial bus (“USB”) circuit for boosting a signal on a USB bus disclosed. The circuit includes a first stage inverting buffer coupled to a second stage inverting buffer to form a non-inverting buffer circuit. A high pass filter is coupled in series with the non-inverting buffer circuit to provide AC coupling to the USB bus and to allow fast signal edges through the circuit. The booster circuit is arranged to improve signal quality over a USB bus to allow additional USB devices and longer USB busses to be utilized.

Abstract: Methods, apparatus, and products are disclosed for implementing a redundant array of inexpensive drives (‘RAID’) with an external RAID controller and hard disk drives from separate computers, including configuring by the external RAID controller a RAID array, the RAID array comprising hard disk drives from the separate computers, the external RAID controller comprising a hardware RAID controller installed externally with respect to the separate computers, and storing, by one or more of the separate computers through the external RAID controller, computer data on the RAID array.

Abstract: A system for allowing a designer to implement Universal Serial Bus (USB) 2.0 in topologies not anticipated by a USB 2.0 specification and with reduced channel losses, the system comprising: a bus channel having a plurality of electrical elements; and a boost circuit connected at a predetermined location on the bus channel; a plurality of USB signals transmitted through the system; wherein edges of the plurality of USB signals are boosted without impacting the bi-directional nature of the bus channel.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is described for resetting a HyperTransport link in a blade server, including reassigning, by a blade management module, a gate signal from enabling a transceiver to signaling a HyperTransport link reset; sending, by the blade management module to a reset sync module on an out-of-band bus, the gate signal; and in response to the gate signal, sending, by the reset sync module to the blade processor, HyperTransport reset signals. The HyperTransport link includes a bidirectional, serial/parallel, high-bandwidth, low-latency, point to point data communications link. The blade server includes the blade processor, the reset sync module, and the baseboard management controller. The blade server is installed in the blade center. The blade center includes the blade management module. The blade management module is coupled to the baseboard management controller by the blade communication bus.

Abstract: Methods, apparatus, and computer program products are described for resetting a HyperTransport link in a blade server, including reassigning, by a blade management module, a gate signal from enabling a transceiver to signaling a HyperTransport link reset; sending, by the blade management module to a reset sync module on an out-of-band bus, the gate signal; and in response to the gate signal, sending, by the reset sync module to the blade processor, HyperTransport reset signals. The HyperTransport link includes a bidirectional, serial/parallel, high-bandwidth, low-latency, point to point data communications link. The blade server includes the blade processor, the reset sync module, and the baseboard management controller. The blade server is installed in the blade center. The blade center includes the blade management module. The blade management module is coupled to the baseboard management controller by the blade communication bus.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to via structure utilization in a PCB design and provide a novel and non-obvious method, system and computer program product for impedance discontinuity remediation for via stubs and connectors in a PCB. In one embodiment a method for impedance discontinuity remediation in a PCB can be provided. The method can include configuring a pre-distortion filter to negate an impedance discontinuity in an electrical signal caused by a transmission line with one of a via stub or a connector. The method further can include pre-distortion filtering an electrical signal before transmitting the electrical signal over the transmission line. Finally, the method can include transmitting the pre-distortion filtered electrical signal over the transmission line.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is for securing of leased resources on a computer. The design structure includes a computer for securing resources may comprise at least one processor, a plurality of resources, wherein each resource is associated with configuration data and a programmable logic device connected to each of the plurality of resources. The programmable logic device may be configured for determining whether a resource is leased, reading un-encoded configuration data from a resource, and sending the configuration data to a first unit, if the resource is not leased. The programmable logic device may further be configured for reading encoded configuration data from a resource, decoding the configuration data, sending the configuration data that was decoded to a first unit, and logging use of the resource by the first unit, if the resource is leased.

Abstract: A bi-directional universal serial bus (“USB”) circuit for boosting a signal on a USB bus disclosed. The circuit includes a first stage inverting buffer coupled to a second stage inverting buffer to form a non-inverting buffer circuit. A high pass filter is coupled in series with the non-inverting buffer circuit to provide AC coupling to the USB bus and to allow fast signal edges through the circuit. The booster circuit is arranged to improve signal quality over a USB bus to allow additional USB devices and longer USB busses to be utilized.

Abstract: Methods and systems are disclosed for providing independent clock failover for scalable blade servers that include assigning a server blade to one of a plurality of clock failover groups, providing a plurality of independent clock signals to the clock generator of the server blade, wherein one of the plurality of independent clock signals is an active clock signal, detecting a failover condition for the clock failover group assigned to the server blade, and switching the active clock signal, in response to the detected failover condition, from one independent clock signal to another independent clock signal.