Patents by Inventor Jyh Huei Chen

Jyh Huei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210043499
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate electrode layer formed over a substrate, and a gate spacer adjacent to the gate electrode layer. The semiconductor device structure includes a source/drain contact structure formed over the substrate and adjacent to the gate electrode layer. An air gap is formed between the gate spacer and the source/drain contact structure, and the air gap is in direct contact with the gate spacer.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chiang TSAI, Fu-Hsiang SU, Ke-Jing YU, Jyh-Huei CHEN
  • Patent number: 10879400
    Abstract: Field effect transistor and manufacturing method thereof are disclosed. Field effect transistor includes a substrate, a fin, spacers, a gate structure, a hard mask pattern, an insulating layer, and a gate contact. The fin protrudes from the substrate and extends in a first direction. The spacers run in parallel over the fin and extending in a second direction perpendicular to the first direction. The gate structure extends between the spacers and covers the fin. The hard mask pattern covers the gate structure and extends in between the spacers. The insulating layer is disposed over the substrate and covers the hard mask pattern, the gate structure and the spacers. The gate contact penetrates the insulating layer and physically contacts the gate structure. A bottom surface of the gate contact is coplanar with top surfaces of the spacers and the hard mask pattern.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chiang Tsai, Jyh-Huei Chen, Fu-Hsiang Su
  • Patent number: 10868184
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and a gate structure formed over the fin structure. The FinFET device structure also includes a contact formed over the fin structure and adjacent to the gate structure. The FinFET device structure further includes a first hard mask layer formed over the gate structure, and an upper portion of the first hard mask layer has an inverted-T shape. In addition, the FinFET device structure includes a second hard mask layer formed over the contact, and the second hard mask layer has a T shape.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Ho Chiang, Cheng-Han Wu, Jyh-Huei Chen, Jhon-Jhy Liaw
  • Publication number: 20200365698
    Abstract: FinFET devices with source/drain contacts with reduced resistance/capacitance power loss and with an enhanced processing window between the source/drain contacts and a gate via and methods of manufacture are described herein. A metal riser may be formed in a first recess of a source/drain contact of a first material. The metal riser and a contact via may be formed from a second material and the contact via may be formed over the metal riser to provide a hybrid source/drain contact of a finFET with a wide surface contact area at an interface between the source/drain contact and the metal riser. A dielectric fill material and/or a conformal contact etch stop layer may be used to form an isolation region in a second recess of the source/drain contact to extend a processing window disposed between the isolation region and a gate contact of the finFET.
    Type: Application
    Filed: May 17, 2019
    Publication date: November 19, 2020
    Inventors: Kuo-Chiang Tsai, Jyh-Huei Chen
  • Patent number: 10840189
    Abstract: Methods of fabricating an integrated circuit device are provided. The integrated circuit device includes a transistor formed on a substrate. The transistor includes a source region, a drain region, and a gate structure between the source region and the drain region. The integrated circuit device also includes a first dielectric layer over the transistor and a first via contact partially in the first dielectric layer and electrically connected to the source region. The integrated circuit device further includes a second via contact partially in the first dielectric layer and electrically connected to the gate structure. In addition, the upper portion of the first via contact and the upper portion of the second via contact protrude from the first dielectric layer.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chiang Tsai, Jyh-Huei Chen, Jye-Yen Cheng
  • Publication number: 20200350416
    Abstract: A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.
    Type: Application
    Filed: July 13, 2020
    Publication date: November 5, 2020
    Inventors: Chia-Ming HSU, Pei-Yu CHOU, Chih-Pin TSAO, Kuang-Yuan HSU, Jyh-Huei CHEN
  • Patent number: 10825721
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack formed over a semiconductor substrate, a source/drain contact structure laterally adjacent to the gate stack, and a gate spacer formed between the gate stack and the source/drain contact structure. The semiconductor device structure also includes a first insulating capping feature covering the upper surface of the gate stack, a second insulating capping feature covering the upper surface of the source/drain contact structure, and an insulating layer covering the upper surfaces of the first insulating capping feature and the second insulating capping feature. The second insulating capping feature includes a material that is different from the material of the first insulating capping feature. The semiconductor device structure also includes a via structure passing through the insulating layer and the first insulating capping feature and electrically connected to the gate stack.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: November 3, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chiang Tsai, Fu-Hsiang Su, Ke-Jing Yu, Jyh-Huei Chen
  • Publication number: 20200321460
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an insulating layer over a substrate, a gate stack formed in the insulating layer, and an insulating capping layer formed in the insulating layer to cover the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack. The source/drain contact structure has a sidewall that is in direct contact with a sidewall of the insulating capping layer, and an upper surface that is substantially level with an upper surface of the insulating capping layer and an upper surface of the insulating layer. In addition, the semiconductor device structure includes a first via structure above and electrically connected to the gate stack and a second via structure above and electrically connected to the source/drain contact structure.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chiang TSAI, Fu-Hsiang SU, Ke-Jing YU, Chih-Hong HWANG, Jyh-Huei CHEN
  • Publication number: 20200279774
    Abstract: A semiconductor device includes a substrate, a first gate structure and a second gate structure over the substrate, a first hard mask on a top surface of the first gate structure, a second hard mask on the second gate structure and a third hard mask disposed between the first gate structure and the second gate structure and disposed between the first hard mask and the second hard mask. A bottom surface of the third hard mask is substantially flush with a bottom surface of the first gate structure.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Hsiang Su, Jyh-Huei Chen, Kuo-Chiang Tsai, Ke-Jing Yu
  • Patent number: 10714586
    Abstract: A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ming Hsu, Pei-Yu Chou, Chih-Pin Tsao, Kuang-Yuan Hsu, Jyh-Huei Chen
  • Publication number: 20200203531
    Abstract: Field effect transistor and manufacturing method thereof are disclosed. Field effect transistor includes a substrate, a fin, spacers, a gate structure, a hard mask pattern, an insulating layer, and a gate contact. The fin protrudes from the substrate and extends in a first direction. The spacers run in parallel over the fin and extending in a second direction perpendicular to the first direction. The gate structure extends between the spacers and covers the fin. The hard mask pattern covers the gate structure and extends in between the spacers. The insulating layer is disposed over the substrate and covers the hard mask pattern, the gate structure and the spacers. The gate contact penetrates the insulating layer and physically contacts the gate structure. A bottom surface of the gate contact is coplanar with top surfaces of the spacers and the hard mask pattern.
    Type: Application
    Filed: December 24, 2018
    Publication date: June 25, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chiang Tsai, Jyh-Huei Chen, Fu-Hsiang Su
  • Patent number: 10693004
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a substrate and an insulating capping layer over the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack and having an upper surface that is substantially level with the upper surface of the insulating capping layer. The semiconductor device structure also includes a first via structure passing through the insulating capping layer and electrically connected to the gate stack, and a second via structure above and electrically connected to the source/drain contact structure. The first via structure and the second via structure have different vertical heights.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufactruing Co., Ltd.
    Inventors: Kuo-Chiang Tsai, Fu-Hsiang Su, Ke-Jing Yu, Chih-Hong Hwang, Jyh-Huei Chen
  • Publication number: 20200168502
    Abstract: In one example, a method includes performing a first etching process to pattern a dielectric layer and expose a contact etch stop layer, performing a second etching process to remove the etch stop layer and expose a top surface of an underlying feature, performing a third etching process to laterally recess the etch stop layer, and depositing a conductive material over the underlying feature to create a conductive feature in direct contact with the underlying feature.
    Type: Application
    Filed: April 1, 2019
    Publication date: May 28, 2020
    Inventors: Kuo-Chiang Tsai, Jyh-Huei Chen
  • Patent number: 10658237
    Abstract: Semiconductor devices are provided, and includes a substrate, a first gate structure and a second gate structure over the substrate, a first hard mask on the first gate structure and a second hard mask on the second gate structure and a third hard mask. The third hard mask is disposed in a dielectric layer between the first gate structure and the second gate structure and disposed between the first hard mask and the second hard mask.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Hsiang Su, Jyh-Huei Chen, Kuo-Chiang Tsai, Ke-Jing Yu
  • Publication number: 20200135912
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack formed over a semiconductor substrate, a source/drain contact structure adjacent to the gate stack, and a gate spacer formed between the gate stack and the source/drain contact structure. The semiconductor device structure also includes a first insulating capping feature covering an upper surface of the gate stack, a second insulating capping feature covering an upper surface of the source/drain contact structure, and an insulating layer covering the upper surfaces of the first insulating capping feature and the second insulating capping feature. The second insulating capping feature includes a material that is different from a material of the first insulating capping feature. The semiconductor device structure also includes a via structure passing through the insulating layer and the first insulating capping feature and electrically connected to the gate stack.
    Type: Application
    Filed: October 26, 2018
    Publication date: April 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chiang TSAI, Fu-Hsiang SU, Yi-Ju CHEN, Jyh-Huei CHEN
  • Publication number: 20200126857
    Abstract: A source/drain region is disposed in a substrate. A gate structure is disposed over the substrate. A gate spacer is disposed on a sidewall of the gate structure. The gate spacer and the gate structure have substantially similar heights. A via is disposed over and electrically coupled to: the source/drain region or the gate structure. A mask layer is disposed over the gate spacer. The mask layer has a greater dielectric constant than the gate spacer. A first side of the mask layer is disposed adjacent to the via. A dielectric layer is disposed on a second side of the mask layer, wherein the mask layer is disposed between the dielectric layer and the via.
    Type: Application
    Filed: January 31, 2019
    Publication date: April 23, 2020
    Inventors: Kuo-Chiang Tsai, Ke-Jing Yu, Fu-Hsiang Su, Yi-Ju Chen, Jyh-Huei Chen
  • Publication number: 20200126843
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack formed over a semiconductor substrate, a source/drain contact structure laterally adjacent to the gate stack, and a gate spacer formed between the gate stack and the source/drain contact structure. The semiconductor device structure also includes a first insulating capping feature covering the upper surface of the gate stack, a second insulating capping feature covering the upper surface of the source/drain contact structure, and an insulating layer covering the upper surfaces of the first insulating capping feature and the second insulating capping feature. The second insulating capping feature includes a material that is different from the material of the first insulating capping feature. The semiconductor device structure also includes a via structure passing through the insulating layer and the first insulating capping feature and electrically connected to the gate stack.
    Type: Application
    Filed: November 5, 2018
    Publication date: April 23, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chiang TSAI, Fu-Hsiang SU, Ke-Jing YU, Jyh-Huei CHEN
  • Publication number: 20200105931
    Abstract: A method for forming a FinFET device structure is provided. The method for forming a FinFET device structure includes forming a fin structure over a substrate, and forming a source/drain (S/D) structure over the fin structure. The method for forming a FinFET device structure also includes forming an inter-layer dielectric (ILD) structure covering the S/D structure, and forming a gate structure over the fin structure and adjacent to the S/D structure. The method for forming a FinFET device structure further includes forming a first hard mask layer over the gate structure, and forming a second hard mask layer over the first hard mask layer. In addition, the method for forming a FinFET device structure includes etching the ILD structure to form an opening exposing the S/D structure. The opening and a recess in the second hard mask layer are formed simultaneously.
    Type: Application
    Filed: November 26, 2018
    Publication date: April 2, 2020
    Inventors: Cheng-Han WU, Yu-Ho CHIANG, Jyh-Huei CHEN, Jhon-Jhy LIAW
  • Publication number: 20200058785
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a substrate and an insulating capping layer over the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack and having an upper surface that is substantially level with the upper surface of the insulating capping layer. The semiconductor device structure also includes a first via structure passing through the insulating capping layer and electrically connected to the gate stack, and a second via structure above and electrically connected to the source/drain contact structure. The first via structure and the second via structure have different vertical heights.
    Type: Application
    Filed: October 18, 2018
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chiang TSAI, Fu-Hsiang SU, Ke-Jing YU, Chih-Hong HWANG, Jyh-Huei CHEN
  • Publication number: 20200043787
    Abstract: Semiconductor devices are provided, and includes a substrate, a first gate structure and a second gate structure over the substrate, a first hard mask on the first gate structure and a second hard mask on the second gate structure and a third hard mask. The third hard mask is disposed in a dielectric layer between the first gate structure and the second gate structure and disposed between the first hard mask and the second hard mask.
    Type: Application
    Filed: October 30, 2018
    Publication date: February 6, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Hsiang Su, Jyh-Huei Chen, Kuo-Chiang Tsai, Ke-Jing Yu