Patents by Inventor Jyh Huei Chen
Jyh Huei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10109507Abstract: A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent.Type: GrantFiled: May 31, 2017Date of Patent: October 23, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Jung Liu, Chih-Pin Tsao, Chia-Wei Soong, Jyh-Huei Chen, Shu-Hui Wang, Shih-Hsun Chang
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Patent number: 9941372Abstract: The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an electrode. An exemplary structure for a semiconductor device comprises a semiconductor substrate; an electrode over the semiconductor substrate, wherein the electrode comprises a trench in an upper portion of the electrode; and a dielectric feature in the trench.Type: GrantFiled: May 9, 2016Date of Patent: April 10, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pai-Chieh Wang, Tsung Yao Wen, Jyh-Huei Chen
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Publication number: 20170352559Abstract: A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent.Type: ApplicationFiled: May 31, 2017Publication date: December 7, 2017Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Jung LIU, Chih-Pin TSAO, Chia-Wei SOONG, Jyh-Huei CHEN, Shu-Hui WANG, Shih-Hsun CHANG
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Publication number: 20170222008Abstract: In a method of manufacturing a semiconductor device, a first contact hole is formed in one or more dielectric layers disposed over a source/drain region or a gate electrode. An adhesive layer is formed in the first contact hole. A first metal layer is formed on the adhesive layer in the first contact hole. A silicide layer is formed on an upper surface of the first metal layer. The silicide layer includes a same metal element as the first metal layer.Type: ApplicationFiled: December 14, 2016Publication date: August 3, 2017Inventors: Chia-Ming HSU, Chih-Pin TSAO, Jyh-Huei CHEN, Kuang-Yuan HSU, Pei-Yu CHOU
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Patent number: 9449971Abstract: An embodiment is a method including forming a first fin on a substrate, the first fin having a first longitudinal axis, forming a first trench having a first width in the first fin, the first trench dividing the first fin into at least two fin portions, forming a first gate structure and first source/drain regions over one of the at least two fin portions of the first fin, and forming a second gate structure and second source/drain regions over another of the at least two fin portions of the first fin.Type: GrantFiled: December 1, 2014Date of Patent: September 20, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chiang TIng, Jyh-Huei Chen, Wen-Huei Guo, Cheng-Han Wu, Yu-Wei Lee
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Publication number: 20160254360Abstract: The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an electrode. An exemplary structure for a semiconductor device comprises a semiconductor substrate; an electrode over the semiconductor substrate, wherein the electrode comprises a trench in an upper portion of the electrode; and a dielectric feature in the trench.Type: ApplicationFiled: May 9, 2016Publication date: September 1, 2016Inventors: Pai-Chieh Wang, Tsung Yao Wen, Jyh-Huei Chen
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Publication number: 20160155739Abstract: An embodiment is a method including forming a first fin on a substrate, the first fin having a first longitudinal axis, forming a first trench having a first width in the first fin, the first trench dividing the first fin into at least two fin portions, forming a first gate structure and first source/drain regions over one of the at least two fin portions of the first fin, and forming a second gate structure and second source/drain regions over another of the at least two fin portions of the first fin.Type: ApplicationFiled: December 1, 2014Publication date: June 2, 2016Inventors: Kuo-Chiang Ting, Jyh-Huei Chen, Wen-Huei Guo, Cheng-Han Wu, Yu-Wei Lee
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Patent number: 9356136Abstract: Integrated circuit devices with field effect transistors have source and drain regions that include a first and a second layer. The first layer is formed below the plane of the channel region. The first layer includes doped silicon and carbon that has a crystal lattice structure that is smaller than that of silicon. The second layer is formed over the first layer and rises above the plane of the channel region. The second layer is formed by a material that includes doped epitaxially grown silicon. The second layer has an atomic fraction of carbon less than half that of the first layer. The first layer is formed to a depth at least 10 nm below the surface of the channel region. This structure facilitates the formation of source and drain extension areas that form very shallow junctions. The devices provide sources and drains that have low resistance while being comparatively resistant to short channel effects.Type: GrantFiled: March 7, 2013Date of Patent: May 31, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Yuan Lu, Lilly Su, Chun-Hung Huang, Chii-Horng Li, Jyh-Huei Chen
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Patent number: 9337293Abstract: The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an electrode. An exemplary structure for a semiconductor device comprises a semiconductor substrate; an electrode over the semiconductor substrate, wherein the electrode comprises a trench in an upper portion of the electrode; and a dielectric feature in the trench.Type: GrantFiled: February 22, 2013Date of Patent: May 10, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pai-Chieh Wang, Tsung Yao Wen, Jyh-Huei Chen
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Patent number: 9082789Abstract: An integrated circuit device and method for manufacturing an integrated circuit device is disclosed. The integrated circuit device comprises a core device and an input/output circuit. Each of the core device and input/output circuit includes a PMOS structure and an NMOS structure. Each of the PMOS includes a p-type metallic work function layer over a high-k dielectric layer, and each of the NMOS structure includes an n-type metallic work function layer over a high-k dielectric layer. There is an oxide layer under the high-k dielectric layer in the input/output circuit.Type: GrantFiled: May 13, 2011Date of Patent: July 14, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Hung Huang, Yu-Hsien Lin, Ming-Yi Lin, Jyh-Huei Chen
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Patent number: 8877614Abstract: An embodiment is a semiconductor structure. The semiconductor structure comprises an epitaxial region, a gate structure, a contact spacer, and an etch stop layer. The epitaxial region is in a substrate. A top surface of the epitaxial region is elevated from a top surface of the substrate, and the epitaxial region has a facet between the top surface of the substrate and the top surface of the epitaxial region. The gate structure is on the substrate. The contact spacer is laterally between the facet of the epitaxial region and the gate structure. The etch stop layer is over and adjoins each of the contact spacer and the top surface of the epitaxial region. A ratio of an etch selectivity of the contact spacer to an etch selectivity of the etch stop layer is equal to or less than 3:1.Type: GrantFiled: October 13, 2011Date of Patent: November 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hung Ko, Jyh-Huei Chen, Ming-Jie Huang
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Patent number: 8835242Abstract: An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness.Type: GrantFiled: February 12, 2014Date of Patent: September 16, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hung Ko, Jyh-Huei Chen, Ming-Jie Huang
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Publication number: 20140252468Abstract: Integrated circuit devices with field effect transistors have source and drain regions that include a first and a second layer. The first layer is formed below the plane of the channel region. The first layer includes doped silicon and carbon that has a crystal lattice structure that is smaller than that of silicon. The second layer is formed over the first layer and rises above the plane of the channel region. The second layer is formed by a material that includes doped epitaxially grown silicon. The second layer has an atomic fraction of carbon less than half that of the first layer. The first layer is formed to a depth at least 10 nm below the surface of the channel region. This structure facilitates the formation of source and drain extension areas that form very shallow junctions. The devices provide sources and drains that have low resistance while being comparatively resistant to short channel effects.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Wei-Yuan Lu, Lilly Su, Chun-Hung Huang, Chii-Horng Li, Jyh-Huei Chen
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Publication number: 20140162432Abstract: An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness.Type: ApplicationFiled: February 12, 2014Publication date: June 12, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hung Ko, Jyh-Huei Chen, Ming-Jie Huang
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Patent number: 8735258Abstract: Methods of fabricating a semiconductor device including a metal gate transistor and a resistor are provided. A method includes providing a substrate including a transistor device region and an isolation region, forming a dummy gate over the transistor device region and a resistor over the isolation region, and implanting the resistor with a dopant. The method further includes wet etching the dummy gate to remove the dummy gate, and then forming a metal gate over the transistor device region to replace the dummy gate.Type: GrantFiled: January 5, 2012Date of Patent: May 27, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hung Ko, Jyh-Huei Chen, Shyh-Wei Wang
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Patent number: 8692353Abstract: An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness.Type: GrantFiled: September 2, 2011Date of Patent: April 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hung Ko, Jyh-Huei Chen, Ming-Jie Huang
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Patent number: 8658483Abstract: A method of fabricating an integrated circuit device is provided. The method includes forming a replacement gate structure with a dummy polysilicon layer on a first surface of a substrate. The method further includes depositing a dielectric layer by a thermal process to form offset spacers on two opposing sides of the replacement gate structure, wherein the dielectric layer is deposited on the first surface and a second surface opposing the first surface of the substrate. The method further includes removing the dummy polysilicon layer from the replacement gate structure, wherein the dielectric layer on the second surface of the substrate protects the second surface of the substrate during the removing step.Type: GrantFiled: November 19, 2012Date of Patent: February 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Tzu Hsu, Ching-Chung Pai, Yu-Hsien Lin, Jyh-Huei Chen
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Patent number: 8569141Abstract: A method includes forming a polysilicon layer over a substrate, forming a hard mask over the polysilicon layer, and doping a first portion of the hard mask with a dopant to form a doped hard mask region, wherein a second portion of the hard mask is not doped with the dopant. An etching step is performed to etch the first and the second portions of the hard mask, wherein the second portion of the hard mask is removed, and wherein at least a bottom portion of the doped hard mask region is not removed. After the etching step, the bottom portion of the doped hard mask region is removed. Electrical connections are formed to connect to a portion of the polysilicon layer in order to form a resistor.Type: GrantFiled: August 31, 2011Date of Patent: October 29, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hung Huang, Jyh-Huei Chen
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Publication number: 20130178039Abstract: Methods of fabricating a semiconductor device including a metal gate transistor and a resistor are provided. A method includes providing a substrate including a transistor device region and an isolation region, forming a dummy gate over the transistor device region and a resistor over the isolation region, and implanting the resistor with a dopant. The method further includes wet etching the dummy gate to remove the dummy gate, and then forming a metal gate over the transistor device region to replace the dummy gate.Type: ApplicationFiled: January 5, 2012Publication date: July 11, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Hung Ko, Jyh-Huei Chen, Shyh-Wei Wang
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Publication number: 20130092985Abstract: An embodiment is a semiconductor structure. The semiconductor structure comprises an epitaxial region, a gate structure, a contact spacer, and an etch stop layer. The epitaxial region is in a substrate. A top surface of the epitaxial region is elevated from a top surface of the substrate, and the epitaxial region has a facet between the top surface of the substrate and the top surface of the epitaxial region. The gate structure is on the substrate. The contact spacer is laterally between the facet of the epitaxial region and the gate structure. The etch stop layer is over and adjoins each of the contact spacer and the top surface of the epitaxial region. A ratio of an etch selectivity of the contact spacer to an etch selectivity of the etch stop layer is equal to or less than 3:1.Type: ApplicationFiled: October 13, 2011Publication date: April 18, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hung Ko, Jyh-Huei Chen, Ming-Jie Huang