Abstract: A method provides adaptive interrupt latency to improve performance in a processing system. A ration of transmit queue depth to receive queue depth of the adapter is compared to its historical value in order to provide an estimate of processor load. The estimated processor load is then used to set a parameter that controls the frequency of an interrupt generator, which may be controlled by setting an interrupt queue depth threshold, packet frequency threshold or interrupt hold-off time value. The historical value may be predetermined, user-settable, obtained during a calibration interval or obtained by taking a long-term average of the ratio.

Abstract: A mechanism is provided for biasing placement of a software thread on a currently idle and dispatched processor. The operating system starts with the last logical processor on which the software thread ran and determines whether that processor is idle and dispatched and considers each logical processor until a currently dispatched and idle logical processor is found. If a currently dispatched and idle logical processor is not found, then the operating system biases placing the software thread on an idle logical processor.

Abstract: Methods for injecting diluents into a gas turbine assembly of an integrated combined-cycle (IGCC) plant are disclosed. Specifically, the methods include injecting a diluent into an air stream to dilute the oxygen content of the air stream; and channeling the diluted air stream into a main air compressor for compression.

Abstract: Improving system resource utilization in a data processing system is provided. A determination is made as to whether there is at least one ceded virtual processor in a plurality of virtual processors in a shared resource pool. Responsive to existence of the at least one ceded virtual processor, a determination is made as to whether there is at least one dedicated logical partition configured for a hybrid mode. Responsive to identifying at least one hybrid configured dedicated logical partition, a determination is made as to whether the at least one hybrid configured dedicated logical partition requires additional virtual processor cycles. If the at least one hybrid configured dedicated logical partition requiring additional virtual processor cycles, the at least one ceded virtual processor is deallocated from the plurality of virtual processors and allocated to a surrogate resource pool for use by the at least one hybrid configured dedicated logical partition.

Abstract: The present invention provides compounds for modulating receptor kinase activity, particularly ephrin and EGFR, and methods of treating diseases mediated by receptor kinase activity utilizing the compounds and pharmaceutical compositions thereof. Diseases mediated by receptor kinase activity include, but are not limited to, diseases characterized in part by abnormal levels of cell proliferation (i.e. tumor growth), programmed cell death (apoptosis), cell migration and invasion and angiogenesis associated with tumor growth. Compounds of the invention include “spectrum selective” kinase modulators, compounds that inhibit, regulate and/or modulate signal transduction across subfamilies of receptor-type tyrosine kinases, including ephrin and EGFR.

Abstract: The present invention provides a computer implemented method, data processing system, and computer program product for mapping and dispatching virtual processors in a data processing system having at least a first partition and a second partition. The data processing system runs a first partition on a virtual processor during a first timeslice. The data processing system identifies an at least one physical page used by the first partition and the second partition. The data processing system maps the at least one physical page to the first partition and the second partition. The data processing system determines a fitness value based on the mapping. The data processing system dispatches the Virtual processor to the second partition on a second timeslice based on the fitness value, wherein the second timeslice immediately succeeds after the first timeslice, whereby the at least one physical page remains in cache during at least the first timeslice and the second timeslice.

Abstract: A method, a system, and computer readable program code for managing cache coherence in a virtual machine managed system are provided. In response to a processor issuing a message to be broadcast, a determination is made as to whether the processor is part of a virtual domain. In response to a determination that the processor is part of the virtual domain, the message and a first bit mask are sent from a source node to a destination node. In response to receiving the message and the first bit mask, one of a primary link or a secondary link is selected to send the message and the first bit mask over, forming a selected link. The message and the first bit mask are sent to the destination node over the selected link.

Abstract: The invention generally relates to electronic collaboration sessions and, more particularly, to systems and methods for providing reconnection to and migration of electronic collaboration sessions. A method for managing a collaboration session includes providing a computer infrastructure structured and arranged to store data regarding a plurality of clients of a collaboration session, and monitor a connection of each of the plurality of clients to a host system. The computer infrastructure is further operable to (i) migrate the plurality of clients to a new host system after determining that a number of the plurality of clients experiencing connection problems with the first host system exceeds a threshold value and/or (ii) present customized summary data to at least one of the plurality of clients after the at least one of the plurality of clients reconnects to the collaboration session after having been disconnected from the collaboration session.

Abstract: Illustrated embodiments provide a computer implemented method and data processing system for redispatching a partition by tracking a set of memory pages, belonging to the dispatched partition. In one illustrative embodiment the computer implemented method comprises finding an effective page address to real page address mapping for a page address miss to create a found real page address and page size combination, responsive to determining the page address miss in a page addressing buffer, and saving the found real page address and page size combination as an entry in set of entries in an array. Further in the computer implemented method, creating a preserved array from the array, responsive to determining the dispatched partition to be an undispatched partition.

Abstract: A method, computer program product, and a data processing system for data prioritization in a multi-tier network system is provided. A server having a plurality of processors receives data from a client. A priority of the client is then identified. Responsive to identifying the priority, the data is queued in a queue of a first plurality of queues associated with a first processor of the plurality of processors. The queue is one of a plurality of queues associated with the first processor and is associated with the priority.

Abstract: Methods and apparatus are provided for virtualizing resources including peripheral components and peripheral interfaces. Peripheral component such as hardware accelerators and peripheral interfaces such as port adapters are offloaded from individual servers onto a resource virtualization switch. Multiple servers are connected to the resource virtualization switch over an I/O bus fabric such as PCI Express or PCI-AS. The resource virtualization switch allows efficient access, sharing, management, and allocation of resources.

Abstract: An intrusion detection mechanism is provided for flexible, automatic, thorough, and consistent security checking and vulnerability resolution in a heterogeneous environment. The mechanism may provide a predefined number of default intrusion analysis approaches, such as signature-based, anomaly-based, scan-based, and danger theory. The intrusion detection mechanism also allows a limitless number of intrusion analysis approaches to be added on the fly. Using an intrusion detection skin, the mechanism allows various weights to be assigned to specific intrusion analysis approaches. The mechanism may adjust these weights dynamically. The score ration can be tailored to determine if an intrusion occurred and adjusted dynamically. Also, multiple security policies for any type of computing element may be enforced.

Abstract: A method, computer program product, and a data processing system for data prioritization in a multi-tier network system is provided. A server having a plurality of processors receives data from a client. A priority of the client is then identified. Responsive to identifying the priority, the data is queued in a queue of a first plurality of queues associated with a first processor of the plurality of processors. The queue is one of a plurality of queues associated with the first processor and is associated with the priority. Additionally, mechanisms for reassigning connection capacity from one priority class to another priority class at the network layer in a multi-tier network system is provided. As the capacity of connections of one priority class approaches saturation, spare capacity may be reassigned from another class to the priority class approaching saturation between the first-tier systems.

Abstract: An intrusion detection mechanism is provided for flexible, automatic, thorough, and consistent security checking and vulnerability resolution in a heterogeneous environment. The mechanism may provide a predefined number of default intrusion analysis approaches, such as signature-based, anomaly-based, scan-based, and danger theory. The intrusion detection mechanism also allows a limitless number of intrusion analysis approaches to be added on the fly. Using an intrusion detection skin, the mechanism allows various weights to be assigned to specific intrusion analysis approaches. The mechanism may adjust these weights dynamically. The score ration can be tailored to determine if an intrusion occurred and adjusted dynamically. Also, multiple security policies for any type of computing element may be enforced.

Abstract: A network device, such as a router, utilizes a virtual interface to hide the presence of redundant backup physical interfaces from a router control unit. If traffic needs to be redirected from a primary physical interface, the router remaps the virtual interface to the backup physical interface without needing to update routes and select one or more alternative routes due to the need to redirect traffic. Instead, the router control unit redirects network traffic associated with the primary physical interface to the associated backup physical interface. In this manner, delays associated with route updating can be avoided, and a relatively seamless switchover can be achieved from the primary to the backup physical interface.

Abstract: A mechanism is provided for determining whether to use cache affinity as a criterion for software thread dispatching in a shared processor logical partitioning data processing system. The server firmware may store data about when and/or how often logical processors are dispatched. Given these data, the operating system may collect metrics. Using the logical processor metrics, the operating system may determine whether cache affinity is likely to provide a significant performance benefit relative to the cost of dispatching a particular logical processor to the operating system.

Abstract: A memory coherence protocol is provided for using cache line access frequencies to dynamically switch from an invalidation protocol to an update protocol. A frequency access count (FAC) is associated with each line of data in a memory area, such as each cache line in a private cache corresponding to a CPU in a multiprocessor system. Each time the line is accessed, the FAC associated with the line is incremented. When the CPU, or process, receives an invalidate signal for a particular line, the CPU checks the FAC for the line. If the CPU, or process, determines that it is a frequent accessor of a particular line that has been modified by another CPU, or process, the CPU sends an update request in order to obtain the modified data. If the CPU is not a frequent accessor of a line that has been modified, the line is simply invalidated in the CPU's memory area.

Abstract: A computer implemented method, data processing system, and computer usable program code are provided for dispatching virtual processors. A determination is made as to whether a physical processor in a set of physical processors is idle, and, if so, a determination is made as to whether an affinity map for the idle physical processor exists. Responsive to an existence of the affinity map, a determination is made as to whether a virtual processor last mapped to the idle physical processor is ready to run using the affinity map and a dispatch algorithm. Responsive to identifying a ready-to-run virtual processor whose affinity map indicates that the idle physical processor is mapped to this virtual processor in its preceding dispatch, the ready-to-run virtual processor is dispatched to the idle physical processor. Thus, memory affinity is maintained between physical and virtual processors when the memory affinity is not expired.

Abstract: A system and method of improved handling of large pages in a virtual memory system. A data memory management unit (DMMU) detects sequential access of a first sub-page and a second sub-page out of a set of sub-pages that comprise a same large page. Then, the DMMU receives a request for the first sub-page and in response to such a request, the DMMU instructs a pre-fetch engine to pre-fetch at least the second sub-page if the number of detected sequential accesses equals or exceeds a predetermined value.

Abstract: A system and method of improved handling of large pages in a virtual memory system. A data memory management unit (DMMU) detects sequential access of a first sub-page and a second sub-page out of a set of sub-pages that comprise a same large page. Then, the DMMU receives a request for the first sub-page and in response to such a request, the DMMU instructs a pre-fetch engine to pre-fetch at least the second sub-page if the number of detected sequential accesses equals or exceeds a predetermined value.