Abstract: A system and technique for hybrid virtual machine configuration management includes a processor and executable logic to: assign to a first set of virtual resources associated with a virtual machine a first priority, the first set associated with entitled resources for the virtual machine; assign to a second set of virtual resources associated with the virtual machine a second priority lower than the first priority, wherein the first and seconds sets when combined exceed the entitled resources for the virtual machine; map the first set to a first physical resource of a pool of shared physical resources, the pool of shared physical resources allocatable to the first and second sets, wherein the first physical resource comprises a desired affinity level to a second physical resource allocated to the virtual machine; and preferentially allocate the first physical resource to the first set of virtual resources.

Abstract: An apparatus includes a processor and a volatile memory that is configured to be accessible in an active memory sharing configuration. The apparatus includes a machine-readable encoded with instructions executable by the processor. The instructions including first virtual machine instructions configured to access the volatile memory with a first virtual machine. The instructions including second virtual machine instructions configured to access the volatile memory with a second virtual machine. The instructions including virtual machine monitor instructions configured to page data out from a shared memory to a reserved memory section in the volatile memory responsive to the first virtual machine or the second virtual machine paging the data out from the shared memory or paging the data in to the shared memory. The shared memory is shared across the first virtual machine and the second virtual machine. The volatile memory includes the shared memory.

Abstract: Illustrated embodiments provide a computer implemented method and data processing system for redispatching a partition by tracking a set of memory pages, belonging to the dispatched partition. In one illustrative embodiment the computer implemented method comprises finding an effective page address to real page address mapping for a page address miss in response to determining the page address miss in a page addressing buffer, and saving the mapping as an entry in an array. The computer implemented method creates a preserved array from the array in response to determining the dispatched partition to be an undispatched partition. The computer implemented method further analyzes of the preserved array for a compressed page in response to determining the undispatched partition is now redispatched, and decompresses the compressed page prior to the partition being redispatched.

Abstract: A set of instructions for implementation in a floating-point unit or other computer processor hardware is disclosed herein. In one embodiment, an extended-range fused multiply-add operation, a first look-up operation, and a second look-up operation are each embodied in hardware instructions configured to be operably executed in a processor. These operations are accompanied by a table which provides a set of defined values in response to various function types, supporting the computation of elementary functions such as reciprocal, square, cube, fourth roots and their reciprocals, exponential, and logarithmic functions. By allowing each of these functions to be computed with a hardware instruction, branching and predicated execution may be reduced or eliminated, while also permitting the use of distributed instructions across a number of execution units.

Abstract: In a NUMA-topology computer system that includes multiple nodes and multiple logical partitions, some of which may be dedicated and others of which are shared, NUMA optimizations are enabled in shared logical partitions. This is done by specifying a home node parameter in each virtual processor assigned to a logical partition. When a task is created by an operating system in a shared logical partition, a home node is assigned to the task, and the operating system attempts to assign the task to a virtual processor that has a home node that matches the home node for the task. The partition manager then attempts to assign virtual processors to their corresponding home nodes. If this can be done, NUMA optimizations may be performed without the risk of reducing the performance of the shared logical partition.

Abstract: Disclosed are microfluidic devices and systems for the desalination of water. The devices and systems can include an electrode configured to generate an electric field gradient in proximity to an intersection formed by the divergence of two microfluidic channels from an inlet channel. Under an applied bias and in the presence of a pressure driven flow of saltwater, the electric field gradient can preferentially direct ions in saltwater into one of the diverging microfluidic channels, while desalted water flows into second diverging channel. Also provided are methods of using the devices and systems described herein to decrease the salinity of water.

Abstract: According to one aspect of the present disclosure, a method and technique for hybrid virtual machine configuration management is disclosed. The method includes: assigning to a first set of virtual resources associated with entitled resources of a virtual machine a first priority; assigning to a second set of virtual resources associated with the virtual machine a second priority lower than the first priority, wherein the first and seconds sets when combined exceed the entitled resources for the virtual machine; mapping the first set of virtual resources to a first physical resource of a pool of shared physical resources allocatable to the first and second sets of virtual resources, wherein the first physical resource comprises a desired affinity level to a second physical resource allocated to the virtual machine; and preferentially allocating the first physical resource to the first set of virtual resources.

Abstract: A system and technique for hybrid virtual machine configuration management includes a processor and executable logic to: assign to a first set of virtual resources associated with a virtual machine a first priority, the first set associated with entitled resources for the virtual machine; assign to a second set of virtual resources associated with the virtual machine a second priority lower than the first priority, wherein the first and seconds sets when combined exceed the entitled resources for the virtual machine; map the first set to a first physical resource of a pool of shared physical resources, the pool of shared physical resources allocatable to the first and second sets, wherein the first physical resource comprises a desired affinity level to a second physical resource allocated to the virtual machine; and preferentially allocate the first physical resource to the first set of virtual resources.

Abstract: The present invention provides compounds for modulating receptor kinase activity, particularly ephrin and EGFR, and methods of treating diseases mediated by receptor kinase activity utilizing the compounds and pharmaceutical compositions thereof. Diseases mediated by receptor kinase activity include, but are not limited to, diseases characterized in part by abnormal levels of cell proliferation (i.e. tumor growth), programmed cell death (apoptosis), cell migration and invasion and angiogenesis associated with tumor growth. Compounds of the invention include “spectrum selective” kinase modulators, compounds that inhibit, regulate and/or modulate signal transduction across subfamilies of receptor-type tyrosine kinases, including ephrin and EGFR.

Abstract: A method, a system and a computer program product for controlling the hardware priority of hardware threads in a data processing system. A Thread Priority Control (TPC) utility assigns a primary level and one or more secondary levels of hardware priority to a hardware thread. When a hardware thread initiates execution in the absence of a system call, the TPC utility enables execution based on the primary level. When the hardware thread initiates execution within a system call, the TPC utility dynamically adjusts execution from the primary level to the secondary level associated with the system call. The TPC utility adjusts hardware priority levels in order to: (a) raise the hardware priority of one hardware thread relative to another; (b) reduce energy consumed by the hardware thread; and (c) fulfill requirements of time critical hardware sections.

Abstract: The present invention provides compounds for modulating receptor kinase activity, particularly ephrin and EGFR, and methods of treating diseases mediated by receptor kinase activity utilizing the compounds and pharmaceutical compositions thereof. Diseases mediated by receptor kinase activity include, but are not limited to, diseases characterized in part by abnormal levels of cell proliferation (i.e. tumor growth), programmed cell death (apoptosis), cell migration and invasion and angiogenesis associated with tumor growth. Compounds of the invention include “spectrum selective” kinase modulators, compounds that inhibit, regulate and/or modulate signal transduction across subfamilies of receptor-type tyrosine kinases, including ephrin and EGFR.

Abstract: Methods of bit manipulation within a computer processor are disclosed. Improved flexibility in bit manipulation proves helpful in computing elementary functions critical to the performance of many programs and for other applications. In one embodiment, a unit of input data is shifted/rotated and multiple non-contiguous bit fields from the unit of input data are inserted in an output register. In another embodiment, one of two units of input data is optionally shifted or rotated, the two units of input data are partitioned into a plurality of bit fields, bitwise operations are performed on each bit field, and pairs of bit fields are combined with either an AND or an OR bitwise operation. Embodiments are also disclosed to simultaneously perform these processes on multiple units and pairs of units of input data in a Single Input, Multiple Data processing environment capable of performing logical operations on floating point data.

Abstract: A technique for determining placement fitness for partitions under a hypervisor in a host computing system having non-uniform memory access (NUMA) nodes. In an embodiment, a partition resource specification is received from a partition score requester. The partition resource specification identifies a set of computing resources needed for a virtual machine partition to be created by a hypervisor in the host computing system. Resource availability within the NUMA nodes of the host computing system is assessed to determine possible partition placement options. A partition fitness score of a most suitable one of the partition placement options is calculated. The partition fitness score is reported to the partition score requester.

Abstract: A technique for determining placement fitness for partitions under a hypervisor in a host computing system having non-uniform memory access (NUMA) nodes. In an embodiment, a partition resource specification is received from a partition score requester. The partition resource specification identifies a set of computing resources needed for a virtual machine partition to be created by a hypervisor in the host computing system. Resource availability within the NUMA nodes of the host computing system is assessed to determine possible partition placement options. A partition fitness score of a most suitable one of the partition placement options is calculated. The partition fitness score is reported to the partition score requester.

Abstract: Two or more processors that each provides a specified thread to access a shared resource that can only be accessed by one thread at a given time. A locking mechanism enables one of the threads to access the shared resource while other threads are retained in a waiting queue. Responsive to an additional thread that is not one of the specified threads being provided access the shared resource during an identified time period, and responsive to a first criterion an a second criterion being met, the additional thread accesses the shared resource before the other threads in the waiting queue.

Abstract: In a NUMA-topology computer system that includes multiple nodes and multiple logical partitions, some of which may be dedicated and others of which are shared, NUMA optimizations are enabled in shared logical partitions. This is done by specifying a home node parameter in each virtual processor assigned to a logical partition. When a task is created by an operating system in a shared logical partition, a home node is assigned to the task, and the operating system attempts to assign the task to a virtual processor that has a home node that matches the home node for the task. The partition manager then attempts to assign virtual processors to their corresponding home nodes. If this can be done, NUMA optimizations may be performed without the risk of reducing the performance of the shared logical partition.

Abstract: Handling requests for power reduction by first enabling a request for an amount of power change, e.g. reduction by any partition. In response to the request for power reduction, an equal proportion of the whole amount of power reduction is distributed between each of a set of cores providing the entitlements to the partitions, and the entitlement of the requesting partition is reduced by an amount corresponding to the whole amount of the power change.

Abstract: An apparatus includes a processor and a volatile memory that is configured to be accessible in an active memory sharing configuration. The apparatus includes a machine-readable encoded with instructions executable by the processor. The instructions including first virtual machine instructions configured to access the volatile memory with a first virtual machine. The instructions including second virtual machine instructions configured to access the volatile memory with a second virtual machine. The instructions including virtual machine monitor instructions configured to page data out from a shared memory to a reserved memory section in the volatile memory responsive to the first virtual machine or the second virtual machine paging the data out from the shared memory or paging the data in to the shared memory. The shared memory is shared across the first virtual machine and the second virtual machine. The volatile memory includes the shared memory.

Abstract: A method, programmed medium and system are provided for enabling a core's cache capacity to be increased by using the caches of the disabled or non-enabled cores on the same chip. Caches of disabled or non-enabled cores on a chip are made accessible to store cachelines for those chip cores that have been enabled, thereby extending cache capacity of enabled cores.

Abstract: The invention generally relates to electronic collaboration sessions and, more particularly, to systems and methods for providing reconnection to and migration of electronic collaboration sessions. A method for managing a collaboration session includes providing a computer infrastructure structured and arranged to store data regarding a plurality of clients of a collaboration session, and monitor a connection of each of the plurality of clients to a host system. The computer infrastructure is further operable to (i) migrate the plurality of clients to a new host system after determining that a number of the plurality of clients experiencing connection problems with the first host system exceeds a threshold value and/or (ii) present customized summary data to at least one of the plurality of clients after the at least one of the plurality of clients reconnects to the collaboration session after having been disconnected from the collaboration session.