Patents by Inventor Kai Chen

Kai Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11842922
    Abstract: A method includes depositing a first dielectric layer over a first conductive feature, depositing a first mask layer over the first dielectric layer, and depositing a second mask layer over the first mask layer. A first opening is patterned in the first mask layer and the second mask layer, the first opening having a first width. A second opening is patterned in a bottom surface of the first opening, the second opening extending into the first dielectric layer, the second opening having a second width. The second width is less than the first width. The first opening is extended into the first dielectric layer and the second opening is extended through the first dielectric layer to expose a top surface of the first conductive feature.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Kai Chen, Jei Ming Chen, Tze-Liang Lee
  • Publication number: 20230387712
    Abstract: An electronic device includes a fuel cell, a first switch, a rechargeable battery, a second switch, and a relay. The fuel cell provides a fuel voltage. The first switch provides the fuel voltage to a first node according to a first control signal. The rechargeable battery provides a battery voltage. The second switch is coupled to the first node and charges the rechargeable battery with the fuel voltage according to a second control signal. The relay provides a voltage of the first node to the load according to the third control signal.
    Type: Application
    Filed: September 14, 2022
    Publication date: November 30, 2023
    Inventors: Che-Jung HSU, Cheng-Huei LIN, Yen-Teh SHIH, Yu-Kai CHEN, Min-Min WU
  • Publication number: 20230386595
    Abstract: A random transient power test signal generator based on three-dimensional memristive discrete map, which utilizes a three-dimensional parallel bi-memristor Logistic map module to generate two pseudo-random sequences, and based on the two pseudo-random sequences, uses two waveform output modules to generate a transient voltage signal and a transient current signal respectively, thus the random transient power testing signal is obtained.
    Type: Application
    Filed: August 15, 2023
    Publication date: November 30, 2023
    Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
    Inventors: Bo XU, Yuhua CHENG, Kai CHEN, Jia ZHAO, Hang GENG, Yifan WANG
  • Publication number: 20230386918
    Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 30, 2023
    Inventors: Chun-Hsien Huang, Hong-Mao Lee, Hsien-Lung Yang, Yu-Kai Chen, Wei-Jung Lin
  • Patent number: 11829549
    Abstract: A method of controlling a stylus pen of a touch panel includes steps of: outputting an uplink control signal to a sensing electrode of the touch panel for controlling the stylus pen in an uplink control period; and outputting a direct-current (DC) voltage to a gate line of the touch panel in the uplink control period.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: November 28, 2023
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Hung-Hsiang Chen, Wei-Kai Chen, Huang-Chin Tang
  • Patent number: 11831105
    Abstract: A connector assembly includes an insulative housing, first and second conductive ground wafers (see e.g., 661 and 663) and a plurality of grounding links. The insulative housing has a plurality of conductive signal terminals disposed therein (see e.g., 662). The insulative housing has opposite side surfaces and a plurality of openings therein extending between the side surfaces. The second ground wafer is spaced from and parallel to the first ground wafer. The grounding links are electrically connected to one of the ground wafers and extend towards another of the ground wafers and extend through the openings in the housing.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: November 28, 2023
    Assignee: Molex, LLC
    Inventors: Teng-Kai Chen, John C. Laurx, Li Zhuang
  • Publication number: 20230377873
    Abstract: A semiconductor structure includes a substrate; an isolation structure over the substrate; a first fin extending from the substrate and through the isolation structure; a first source/drain structure over the first fin; a contact etch stop layer over the isolation structure and contacting a first side face of the first source/drain structure; and a first dielectric structure contacting a second side face of the first source/drain structure. The first side face and the second side face are on opposite sides of the first fin in a cross-sectional view cut along a widthwise direction of the first fin. The first dielectric structure extends higher than the first source/drain structure.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 23, 2023
    Inventors: Ming-Chang Wen, Chang-Yun Chang, Hsien-Chin Lin, Hung-Kai Chen
  • Publication number: 20230377897
    Abstract: In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition; depositing a second layer including over 50 atomic percent of silicon; and depositing a photosensitive layer on the second layer. In some implementations, the second layer is deposited by ALD, CVD, or PVD processes.
    Type: Application
    Filed: July 21, 2023
    Publication date: November 23, 2023
    Inventors: Szu-Ping Tung, Chun-Kai Chen, Yi-Nien Su
  • Publication number: 20230369955
    Abstract: A controller for controlling a voltage converter that generates a real-time charging current and a real-time charging voltage, including a compensation circuit, a driving circuit and a control circuit. The compensation circuit compares the real-time charging current with a preset charging current to generate a first comparison result, compares the real-time charging voltage with a preset battery voltage to generate a second comparison result, and generates a compensation voltage. The driving circuit generates a pulse width modulation signal based on the compensation voltage. The control circuit generates a control signal based on the pulse width modulation signal and a current indication signal. The driving circuit further generates a first switching signal based on the pulse width modulation signal to control an upper switch of the voltage converter and generates a second switching signal based on the control signal to control a lower switch of the voltage converter.
    Type: Application
    Filed: May 11, 2023
    Publication date: November 16, 2023
    Inventors: Kai CHEN, Zhiguo LIU
  • Publication number: 20230369382
    Abstract: A stretchable pixel array substrate includes a base, pixel structures and a gate driving circuit electrically connected to the pixel structures. The base has an active area and a peripheral area outside the active area. The peripheral area has openings to define first islands, second islands and first bridges of the peripheral area. An area of each of the first islands is greater than an area of each of the second islands. At least a part of the first bridges is connected between the first islands and the second islands. The pixel structures are disposed on the active area of the base. The gate driving circuit includes first parts disposed on the first islands and second parts disposed on the second islands and electrically connected to the first parts.
    Type: Application
    Filed: August 5, 2022
    Publication date: November 16, 2023
    Applicant: AUO Corporation
    Inventors: Kent-Yi Lee, Wen-Ting Wang, Chia-Kai Chen, Chih-Ling Hsueh
  • Patent number: 11816053
    Abstract: A reconfigurable data acquisition card including at least one field programmable gate array (FPGA) and a configurable bus switch coupled with the FPGA. The bus switch forms at least first and second ports used by the FPGA, the bus switch being adaptable for insertion into a connection having a number of lanes at least equal to a combined number of lanes in the first and second ports. The data acquisition card further includes multiple optical transmitters and optical receivers. Each optical transmitter and optical receiver is coupled with a corresponding transceiver in the FPGA via at least one optical fiber having multiple communication links. Timing circuitry in the data acquisition card is coupled with clock generation and distribution circuitry in the FPGA and is configured to distribute clock and timing signals to detector front-ends with fixed latency and to synchronize input/output links with a system clock generated by the FPGA.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: November 14, 2023
    Assignee: Brookhaven Science Associates, LLC
    Inventors: Kai Chen, Michael Begel, Hucheng Chen, Francesco Lanni
  • Patent number: 11816506
    Abstract: Systems, devices, media, and methods are presented for throttling (i.e., adjusting) the workload of an application (e.g., number of task requests) in order to improve processor core usage within a heterogeneous multiprocessor system. When high-performance processing is beneficial to the application, the number of task requests may be increased in order to have high-performance processor cores within the heterogeneous multiprocessor system core processor perform the tasks. On the other hand, when high-performance processing is not beneficial, the number of task requests may be decreased in order to have low-performance processor cores within the heterogeneous multiprocessor system perform the tasks. Processor core usage is monitored, and the number of tasks being performed are adjusted to match the processor core usage to a target processor core usage for functions the application is performing.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: November 14, 2023
    Assignee: Snap Inc.
    Inventors: Michael Cieslak, Jiayao Yu, Kai Chen, Farnaz Azmoodeh, Michael David Marr, Jun Huang, Zahra Ferdowsi
  • Patent number: 11816010
    Abstract: Systems, devices, media, and methods are presented for releasing an application feature in incremental stages while monitoring the application for anomalies. The feature includes a package of code and an action setting. The methods in some implementations include identifying active devices on which the application has been installed, monitoring the application according to a set of metrics, activating the feature by changing its action setting for a first segment of the active devices, pausing the feature if an anomaly is detected among the set of metrics, and generating a repair ticket. As long as no anomaly is detected, the activating step proceeds for subsequent segments of the active devices, iteratively, until the release is completed. A feature rank may be used to process and release a plurality of features in order of priority.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: November 14, 2023
    Assignee: Snap Inc.
    Inventors: Michael Cieslak, Jiayao Yu, Kai Chen, Farnaz Azmoodeh, Michael David Marr, Jun Huang, Zahra Ferdowsi, Olamide Valerie Olatunji, David Boyle, Claire Reinert
  • Publication number: 20230362118
    Abstract: An example method comprises: receiving, at the server from a first client device, a request for access to a client feature on the first client device; determining, by the server, an applicable rule for the access request, the applicable rule having a plurality of nodes; determining, by the server, device capabilities needed for the determined rule; determining, by the server, nodes that can be executed and nodes that cannot be executed, based on the device capabilities; executing, by the server, nodes that can be executed to reach a partial decision for the applicable rule; pruning the rule to remove executed nodes and generate a pruned rule that includes nodes that cannot be executed; transmitting the pruned rule and partial decision to the device. The pruned rule is executed on the first client device with partial decision to generate a final decision. The client feature is configured based on the decision.
    Type: Application
    Filed: July 11, 2023
    Publication date: November 9, 2023
    Inventors: Michael Ronald Cieslak, Jiayao Yu, Kai Chen, Farnaz Azmoodeh, Michael David Marr, Jun Huang```, Zahra Ferdowsi
  • Patent number: 11809824
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for computing numeric representations of words. One of the methods includes obtaining a set of training data, wherein the set of training data comprises sequences of words; training a classifier and an embedding function on the set of training data, wherein training the embedding function comprises obtained trained values of the embedding function parameters; processing each word in the vocabulary using the embedding function in accordance with the trained values of the embedding function parameters to generate a respective numerical representation of each word in the vocabulary in the high-dimensional space; and associating each word in the vocabulary with the respective numeric representation of the word in the high-dimensional space.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: November 7, 2023
    Assignee: Google LLC
    Inventors: Tomas Mikolov, Kai Chen, Gregory S. Corrado, Jeffrey A. Dean
  • Publication number: 20230352346
    Abstract: A method for manufacturing a semiconductor device includes forming a metal-including layer over a semiconductor substrate; forming a hydrophobic polymer layer over the metal-including layer; and forming an amphiphilic polymer layer between the metal-including layer and the hydrophobic polymer layer so as to enhance a bonding force therebetween.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Chen LEE, Ren-Kai CHEN, Ying-Liang CHUANG, Ming-Hsi YEH, Kuo-Bin HUANG
  • Patent number: 11803041
    Abstract: The invention provides a prism module and a folded lens. The prism module includes a housing having an accommodation cavity, a prism assembly, a rotation shaft for rotationally connecting the prism assembly and the housing, a driving assembly for driving the prism assembly to rotate around the rotation shaft and a restoring assembly for resetting the prism assembly. The restoring assembly includes a first magnet and a second magnet. The first magnet is fixed on the prism assembly, and the second magnet is fixed on the housing and is set opposite to the first magnet with distance. The prism module of the invention can realize the resetting of the prism assembly, with small space occupation and convenient for assembly.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: October 31, 2023
    Assignee: AAC Optics Solutions Pte. Ltd.
    Inventors: Linzhen Li, Zhuming Chu, Tongming Xu, Houwei Zhao, Kai Chen
  • Publication number: 20230343418
    Abstract: Provided are a method and system for determining a population pharmacokinetic model of propofol and a derivative thereof. The method comprises determining a population pharmacokinetic model of a compound of formula (I) or propofol, wherein an equation of pharmacokinetic parameters in the population pharmacokinetic model of the compound of formula (1) comprises: CL2=exp(4.20+0.349·log(WT/63.9)-0.749·log(TP/72.4)+0.238·SITE+?CLj) ; an equation of pharmacokinetic parameters in the population pharmacokinetic model of propofol comprises: CL2=exp(4.56+?CLj ).
    Type: Application
    Filed: July 30, 2021
    Publication date: October 26, 2023
    Inventors: Xu WANG, Qianqian JI, Kai CHEN, Xiao LIU, Pangke YAN, Nan WU
  • Publication number: 20230343820
    Abstract: A method of forming a semiconductor device includes forming an epitaxial source/drain (S/D) structure adjacent to a gate structure; forming a dielectric structure over the gate and epitaxial S/D structures; forming a trench in the dielectric structure to accessibly expose a portion of the epitaxial S/D structure; forming a contact feature from the portion of the epitaxial S/D structure within the trench; and forming a S/D contact in the trench to be in contact with the contact feature overlying the epitaxial S/D structure. Forming the contact feature includes forming a metallic layer in the trench; performing a thermal process on the metallic layer to form the contact feature, where after the thermal process, metallic residues remain on a sidewall of a spacer of the dielectric structure in the trench; and removing the metallic residues by using a wet etching process, wherein the spacer of the dielectric structure remains substantially intact.
    Type: Application
    Filed: April 21, 2022
    Publication date: October 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ren-Kai Chen, Li-Chen Lee, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Publication number: 20230343574
    Abstract: A quadrupole transmitting window applied by a quadrupole mass filter is characterized by a method that utilizes the noise band of a transmitted chemical noise ion signal. The mass filter may be utilized in a mass spectrometry (MS) system.
    Type: Application
    Filed: April 26, 2022
    Publication date: October 26, 2023
    Inventors: Kai Chen, Kenneth R. Newton, Christian Wisner-Carlson