Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.

Abstract: A package structure including a semiconductor die, an encapsulant, a redistribution structure, and a through insulating via is provided. The first redistribution structure includes an insulating layer and a circuit layer. The semiconductor die is disposed on the first redistribution structure. The semiconductor die includes a semiconductor base, through semiconductor vias, a dielectric layer, and bonding connectors. Through semiconductor vias penetrate through the semiconductor base. The dielectric layer is disposed on a backside of the semiconductor base. The dielectric layer of the semiconductor die is bonded with the insulating layer of the first redistribution structure. The bonding connectors are embedded in the dielectric layer and connected to the through semiconductor vias. The bonding connectors of the semiconductor die are bonded with bonding pads of the circuit layer. The encapsulant is disposed on the first redistribution structure and encapsulates the semiconductor die.

Abstract: A semiconductor package includes a first redistribution circuit structure, a semiconductor die, and an electrically conductive structure. The semiconductor die is disposed over and electrically coupled to the first redistribution circuit structure. The electrically conductive structure connects a non-active side of the semiconductor die to a conductive feature of the first redistribution circuit structure, where the semiconductor die is thermally couped to the first redistribution circuit structure through the electrically conductive structure, and the electrically conductive structure includes a structure of multi-layer with different materials.

Abstract: A package structure includes a first redistribution circuit structure, a semiconductor die, a connecting film, and a second redistribution circuit structure. The first redistribution circuit structure includes a dielectric structure and a routing structure disposed therein, where the dielectric structure includes a trench exposing the routing structure. The semiconductor die is disposed on and electrically coupled to the first redistribution circuit structure. The connecting film is disposed in the trench and between the semiconductor die and the first redistribution circuit structure, and the semiconductor die is thermally coupled to the routing structure through the connecting film.

Abstract: A semiconductor package includes a first substrate and a first semiconductor device. The first semiconductor device is bonded to the first substrate and includes a second substrate, a plurality of first dies and a second die. The first dies are disposed between the first substrate and the second substrate. The second die is surrounded by the first dies. A cavity is formed among the first dies, the first substrate and the second substrate, and a gap is formed between the second die and the first substrate.

Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.

Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.

Abstract: The present disclosure provides a waveguide structure including an optical component. The optical component includes a plurality of grating coupler teeth over a semiconductive substrate and a plurality of grating coupler openings between adjacent grating coupler teeth, wherein the grating coupler openings are configured to receive a light wave. Each of the grating coupler teeth includes a dielectric stack and an etch stopper embedded in the dielectric stack, wherein the etch stopper has a resistance to a fluorine solution that is higher than that of the dielectric stack. A method of manufacturing a semiconductor device is also provided.

Abstract: In some embodiments, the present disclosure relates to a method of forming a metal-insulator-metal (MIM) device. The method may be performed by depositing a bottom electrode layer over a substrate, depositing a dielectric layer over the bottom electrode layer, depositing a top electrode layer over the dielectric layer, and depositing a first titanium getter layer over the top electrode layer. The first titanium getter layer, the top electrode layer, and the dielectric layer are patterned to expose a peripheral portion of the bottom electrode layer. A passivation layer is deposited over the substrate, the first titanium getter layer, and the peripheral portion of the bottom electrode layer.

Abstract: In some embodiments, the present disclosure relates to a metal-insulator-metal (MIM) device. The MIM device includes a substrate, and a first and second electrode stacked over the substrate. A dielectric layer is arranged between the first and second electrodes. Further, the MIM device includes a titanium getter layer that is disposed over the substrate and separated from the dielectric layer by the first electrode. The titanium getter layer has a higher getter capacity for hydrogen than the dielectric layer.

Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a top electrode overlying a substrate. A passivation layer overlies the top electrode. The passivation layer has a step region that continuously contacts and extends from a top surface of the top electrode to sidewalls of the top electrode. A metal frame overlies the passivation layer. The metal frame continuously contacts and extends from a top surface of the passivation layer to upper sidewalls of the passivation layer in the step region. The metal frame has a protrusion that extends through the passivation layer and contacts the top surface of the top electrode.

Abstract: A method of manufacturing an image sensor includes at least the following steps. A storage node is formed in a substrate. A gate dielectric layer, a storage gate electrode, and a first dielectric layer are sequentially formed over the substrate. A portion of the first dielectric layer is removed to form an opening. A protection layer and a shielding layer are sequentially filled into the opening. The protection layer laterally surrounds the shielding layer and at least a portion of the protection layer is located between the storage gate electrode and the shielding layer. A second dielectric layer is formed over the shielding layer.

Abstract: A MEMS device and methods of forming are provided. A dielectric layer of a first substrate is patterned to expose conductive features and a bottom layer through the dielectric layer. A first surface of a second substrate is bonded to the dielectric layer and the second substrate is patterned to form a membrane and a movable element. A cap wafer is bonded to the second substrate, where bonding the cap wafer to the second substrate forms a first sealed cavity comprising the movable element and a second sealed cavity that is partially bounded by the membrane. Portions of the cap wafer are removed to expose the second sealed cavity to ambient pressure.

Abstract: In some embodiments, the present disclosure relates to a metal-insulator-metal (MIM) device. The MIM device includes a substrate, and a first and second electrode stacked over the substrate. A dielectric layer is arranged between the first and second electrodes. Further, the MIM device includes a titanium getter layer that is disposed over the substrate and separated from the dielectric layer by the first electrode. The titanium getter layer has a higher getter capacity for hydrogen than the dielectric layer.

Abstract: A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming a substrate over a micro-electro-mechanical system (MEMS) substrate. The substrate includes a semiconductor via. The method also includes forming a dielectric layer over a top surface of the substrate, and forming a polymer layer over the dielectric layer. The method further includes patterning the polymer layer to form an opening, and the semiconductor via is exposed by the opening. The method includes forming a conductive layer in the opening and over the polymer layer, and forming an under bump metallization (UBM) layer on the conductive layer. The method further includes forming an electrical connector over the UBM layer, wherein the electrical connector is electrically connected to the semiconductor via through the UBM layer.

Abstract: An electronic device includes a capacitor and a passivation layer covering the capacitor. The capacitor includes a first electrode, a dielectric layer disposed over the first electrode and a second electrode disposed over the dielectric layer. An area of the first electrode is greater than an area of the dielectric layer, and the area of the dielectric layer is greater than an area of the second electrode so that a side of the capacitor has a multi-step structure.

Abstract: The present disclosure provides a waveguide structure including an optical component. The optical component includes a plurality of grating coupler teeth over a semiconductive substrate and a plurality of grating coupler openings between adjacent grating coupler teeth, wherein the grating coupler openings are configured to receive a light wave. Each of the grating coupler teeth includes a dielectric stack and an etch stopper embedded in the dielectric stack, wherein the etch stopper has a resistance to a fluorine solution that is higher than that of the dielectric stack. A method of manufacturing a semiconductor device is also provided.

Abstract: A pad structure with a contact via array for high bond structure is provided. In some embodiments, a semiconductor substrate comprises a pad opening. An interconnect structure is under the semiconductor substrate, and comprises an interlayer dielectric (ILD) layer, a wiring layer, and the contact via array. The wiring layer and the contact via array are in the ILD layer. Further, the contact via array borders the wiring layer and is between the wiring layer and the semiconductor substrate. A pad covers the contact via array in the pad opening, and protrudes into the ILD layer to contact the wiring layer on opposite sides of the contact via array. A method for manufacturing the pad structure, as well as an image sensor with the pad structure, are also provided.

Abstract: The present disclosure provides a semiconductor device, including a semiconductive substrate, a dielectric stack disposed over the semiconductive substrate to form a wall of a grating coupler opening, and an etch stopper interfacing with two sublayers of the dielectric stack and partially separating the interface of the two sublayers. The etch stopper has a resistance to a fluorine solution that is higher than that of the two sublayers. A method of manufacturing the semiconductor device is also provided.

Abstract: The present disclosure provides a semiconductor device, including a semiconductive substrate, a dielectric stack disposed over the semiconductive substrate to form a wall of a grating coupler opening, and an etch stopper interfacing with two sublayers of the dielectric stack and partially separating the interface of the two sublayers. The etch stopper has a resistance to a fluorine solution that is higher than that of the two sublayers. A method of manufacturing the semiconductor device is also provided.