Abstract: A layout for a transistor in a standard cell is disclosed. The layout for a transistor includes an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate placed on top of the active region with a distance from an edge of the gate to the first edge being shorter than a distance from the edge of the gate to the second edge of the active region, wherein the active region is of a non-rectangular shape.

Abstract: A layout for a transistor in a standard cell is disclosed. The layout for a transistor comprises an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate placed on top of the active region with a distance from an edge of the gate to the first edge being shorter than a distance from the edge of the gate to the second edge of the active region, wherein the active region is of a non-rectangular shape.

Abstract: An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.

Abstract: A method for integrally forming a metal-oxide-semiconductor (MOS) device and an electrical fuse device on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. A dielectric layer is deposited over the isolation structure and the semiconductor substrate. A metal layer is deposited on the dielectric layer. A polysilicon layer is deposited on the metal layer. The dielectric layer, the metal layer and the polysilicon layer are patterned into a first stack of the dielectric layer, the metal layer and the polysilicon layer on the isolation structure for functioning as the electrical fuse device, and a second stack of the dielectric layer, the metal layer and the polysilicon layer on the semiconductor substrate for functioning as a gate of the MOS device.

Abstract: A method of packaging an organic electroluminescent (OEL) device is provided. In the method, a substrate comprising an OEL component formed thereon is provided first. Thereafter, a cover plate is provided. Afterward, a hydrophilic polymer serving as a desiccant between the substrate and the cover plate is formed. Then, an adhesive between the substrate and the cover plate for sealing the OEL component and the desiccant is formed. Therefore, moisture/oxygen in the package structure is absorbed and removed by the hydrophilic polymer.

Abstract: A MOS transistor structure is disclosed. A gate electrode is disposed on a semiconductor substrate. A first extension of a predetermined impurity type is substantially aligned with the gate electrode in the substrate. A second extension of the predetermined impurity type overlaps with the first extension in the substrate. The first extension has at least one lateral boundary line closer to the gate electrode than that of the second extension. Source and drain regions of the predetermined polarity type overlaps with the first and second extensions in the substrate. The second extension has at least one lateral boundary line closer to the gate electrode than that of the source and drain regions. The source and drain regions are deeper than the second extension, which is deeper than the first extension, so that they collectively reduce lateral abruptness of the source and drain, while maintaining a reduced extension resistance.

Abstract: An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.

Abstract: An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.

Abstract: An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.

Abstract: A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic circuit region of the semiconductor device, the deep trench isolation being filled with an insulative material. The deep trench isolation thereby prevents the propagation of crystal defects generated in the logic circuit region from propagating into the memory storage region.

Abstract: A package structure of an organic electroluminescent (OEL) device and a method of packaging thereof are provided. The package structure includes a substrate, an OEL component, a cover plate, a desiccant and an adhesive. The OEL component is disposed over the substrate. The cover plate is disposed over the substrate. The desiccant is disposed above the substrate or the cover plate. The desiccant includes, for example but not limited to, a hydrophilic polymer. The adhesive is disposed between the substrate and the cover plate, wherein the OEL component and the desiccant are sealed by the substrate, the cover plate and the adhesive. Therefore, moisture/oxygen in the package structure is absorbed and removed by the hydrophilic polymer.

Abstract: A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic circuit region of the semiconductor device, the deep trench isolation being filled with an insulative material. The deep trench isolation thereby prevents the propagation of crystal defects generated in the logic circuit region from propagating into the memory storage region.

Abstract: A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic circuit region of the semiconductor device, the deep trench isolation being filled with an insulative material. The deep trench isolation thereby prevents the propagation of crystal defects generated in the logic circuit region from propagating into the memory storage region.

Abstract: An electrode substrate for an organic electroluminescent device comprises a substrate, an electrode, and at least one buffer pad. In this case, the electrode is disposed on the substrate, and has a plurality of pixel areas. The buffer pad, which is made of nonconductive material, is disposed inside each of the pixel areas. A height difference between the buffer pad and the electrode is predetermined. Furthermore, an organic electroluminescent device, which comprises a substrate, a first electrode, a separating layer, at least one buffer pad, at least one organic functional layer, and a second electrode, is disclosed.

Abstract: An organic electroluminescent panel includes a substrate, a first electrode, a pixel-defining layer, an organic functional layer, and a second electrode. In this case, the first electrode is formed on one side of the substrate, and the pixel-defining layer is formed on the first electrode or on the substrate. A sidewall of the pixel-defining layer has a pattern with variant heights. The organic functional layer is formed between portions of the pixel-defining layer and is positioned on the first electrode. The second electrode is formed on the organic functional layer. Furthermore, an electrode substrate for constructing the panel and a method for manufacturing the electrode substrate are disclosed.

Abstract: An ink jet printing device for manufacturing an organic electroluminescent device. The ink jet printing device includes a chamber, an inkjet unit, and a pressure adjusting unit. The chamber has a space, and a basement is provided inside the space for supporting the organic electroluminescent device. The inkjet unit has a print head, which includes print holes. The print head is set in the chamber and is used to inject ink toward a substrate of the organic electroluminescent device. The pressure adjusting unit connects to the space so as to steady the pressure of the space within a specific value. Furthermore, an ink jet printing method for manufacturing an organic electroluminescent device is also disclosed.

Abstract: An organic light-emitting device having a porous desiccant layer therein and a method for fabricating the same is provided. The porous desiccant layer is manufactured by spreading a liquid desiccant on a surface, forming air bubbles (by activating some vesicant or injecting gas into the liquid desiccant) and curing the liquid desiccant. The porous desiccant comprises solidified hardening glue having bubbles and lots of desiccant particles or powder distributed evenly therein. Some residual vesicant may remain inside the solidified hardening glue after activation. The bubbles inside the porous desiccant enhance the absorption rate and efficiency of the desiccant so that moisture and gaseous oxygen inside the OLED package can be absorbed rapidly.

Abstract: The present invention provides an organic electro-luminescence device and fabricating thereof. The organic electro-luminescence device comprises a substrate, an anode on said substrate, a light-emitting layer on said anode, a cathode on said light-emitting layer, and an ion-doping layer between said cathode and said light-emitting layer, wherein said ion doping layer is Alq3 doped.

Abstract: A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic circuit region of the semiconductor device, the deep trench isolation being filled with an insulative material. The deep trench isolation thereby prevents the propagation of crystal defects generated in the logic circuit region from propagating into the memory storage region.

Abstract: A semiconductor structure having silicon dioxide layers of different thicknesses is fabricated by forming a sacrificial silicon dioxide layer on the surface of a substrate; implanting nitrogen ions through the sacrificial silicon dioxide layer into first areas of the semiconductor substrate; implanting chlorine and/or bromine ions through the sacrificial silicon dioxide layer into second areas of the semiconductor substrate where silicon dioxide having the highest thickness is to be formed; removing the sacrificial silicon dioxide layer; and then growing a layer of silicon dioxide on the surface of the semiconductor substrate. The growth rate of the silicon dioxide will be faster in the areas containing the chlorine and/or bromine ions and therefore the silicon dioxide layer will be thicker in those regions as compared to the silicon dioxide layer in the regions not containing the chlorine and/or bromine ions.