Patents by Inventor Kai Han

Kai Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060289920
    Abstract: An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.
    Type: Application
    Filed: June 22, 2005
    Publication date: December 28, 2006
    Inventors: I-Lu Wu, Kuang-Hsin Chen, Liang-Kai Han
  • Patent number: 7138319
    Abstract: A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic circuit region of the semiconductor device, the deep trench isolation being filled with an insulative material. The deep trench isolation thereby prevents the propagation of crystal defects generated in the logic circuit region from propagating into the memory storage region.
    Type: Grant
    Filed: January 10, 2005
    Date of Patent: November 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Kiang-Kai Han
  • Patent number: 7051016
    Abstract: The invention relates to a method for administrating a data base comprising a document set, a schema and a repository. The data base comprises a structure index, into which a document reference and, assigned to said document reference, at least one structure path reference of the referenced document is mappable as supplementary path reference. Further at least one schema path reference is mappable into the structure index as missing path reference. The invention relates to a data base. The data base is installed for administration by the inventive administration method. The invention relates to a computer system with a storage unit and a central processing unit. The storage unit of the computer system includes a data base, which is administrated according to the invention by means of the central processing unit.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: May 23, 2006
    Assignee: Software AG
    Inventor: Kay Hans-Peter Winkler
  • Publication number: 20050276947
    Abstract: A package structure of an organic electroluminescent (OEL) device and a method of packaging thereof are provided. The package structure includes a substrate, an OEL component, a cover plate, a desiccant and an adhesive. The OEL component is disposed over the substrate. The cover plate is disposed over the substrate. The desiccant is disposed above the substrate or the cover plate. The desiccant includes, for example but not limited to, a hydrophilic polymer. The adhesive is disposed between the substrate and the cover plate, wherein the OEL component and the desiccant are sealed by the substrate, the cover plate and the adhesive. Therefore, moisture/oxygen in the package structure is absorbed and removed by the hydrophilic polymer.
    Type: Application
    Filed: June 15, 2004
    Publication date: December 15, 2005
    Inventors: Ping-Tsung Huang, Hsia-Tsai Hsiao, Yu-Kai Han, Tung-Sheng Cheng, Yen-Hua Lin
  • Publication number: 20050106836
    Abstract: A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic circuit region of the semiconductor device, the deep trench isolation being filled with an insulative material. The deep trench isolation thereby prevents the propagation of crystal defects generated in the logic circuit region from propagating into the memory storage region.
    Type: Application
    Filed: January 10, 2005
    Publication date: May 19, 2005
    Inventors: Tze-Chiang Chen, Liang-Kai Han
  • Patent number: 6885080
    Abstract: A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic circuit region of the semiconductor device, the deep trench isolation being filled with an insulative material. The deep trench isolation thereby prevents the propagation of crystal defects generated in the logic circuit region from propagating into the memory storage region.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: April 26, 2005
    Assignee: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Liang-Kai Han
  • Publication number: 20040123108
    Abstract: Methods and apparatuses for validating a message with a signature. The method may include receiving the message with the signature and carrying out an integrated validation and storing process. The signature may be validated based on a validation algorithm and a key. The received message may be stored in a database. A method for generating a signature for a message may include carrying out an integrated receiving and generating process. The message to be sent may be received and the signature may be generated based on a signing algorithm and a key. The message may be sent with the signature.
    Type: Application
    Filed: September 12, 2003
    Publication date: June 24, 2004
    Inventors: Kay Hans-Peter Winkler, Michael Ulrich Korner, Harald Ralf Schoning, Eckehard Hermann, Rene Kollmorgen, Dieter Hermann Kessler
  • Publication number: 20040090177
    Abstract: An electrode substrate for an organic electroluminescent device comprises a substrate, an electrode, and at least one buffer pad. In this case, the electrode is disposed on the substrate, and has a plurality of pixel areas. The buffer pad, which is made of nonconductive material, is disposed inside each of the pixel areas. A height difference between the buffer pad and the electrode is predetermined. Furthermore, an organic electroluminescent device, which comprises a substrate, a first electrode, a separating layer, at least one buffer pad, at least one organic functional layer, and a second electrode, is disclosed.
    Type: Application
    Filed: October 24, 2003
    Publication date: May 13, 2004
    Inventors: Yu-Kai Han, Hsia-Tsai Hsiao
  • Publication number: 20040090176
    Abstract: An organic electroluminescent panel includes a substrate, a first electrode, a pixel-defining layer, an organic functional layer, and a second electrode. In this case, the first electrode is formed on one side of the substrate, and the pixel-defining layer is formed on the first electrode or on the substrate. A sidewall of the pixel-defining layer has a pattern with variant heights. The organic functional layer is formed between portions of the pixel-defining layer and is positioned on the first electrode. The second electrode is formed on the organic functional layer. Furthermore, an electrode substrate for constructing the panel and a method for manufacturing the electrode substrate are disclosed.
    Type: Application
    Filed: October 24, 2003
    Publication date: May 13, 2004
    Inventors: Yu-Kai Han, Hsia-Tsai Hsiao, Ming-Chung Shih
  • Publication number: 20040086631
    Abstract: An ink jet printing device for manufacturing an organic electroluminescent device. The ink jet printing device includes a chamber, an inkjet unit, and a pressure adjusting unit. The chamber has a space, and a basement is provided inside the space for supporting the organic electroluminescent device. The inkjet unit has a print head, which includes print holes. The print head is set in the chamber and is used to inject ink toward a substrate of the organic electroluminescent device. The pressure adjusting unit connects to the space so as to steady the pressure of the space within a specific value. Furthermore, an ink jet printing method for manufacturing an organic electroluminescent device is also disclosed.
    Type: Application
    Filed: October 22, 2003
    Publication date: May 6, 2004
    Inventors: Yu-Kai Han, Hsia-Tsai Hsiao, Pi-Chun Weng
  • Publication number: 20040082089
    Abstract: An organic light-emitting device having a porous desiccant layer therein and a method for fabricating the same is provided. The porous desiccant layer is manufactured by spreading a liquid desiccant on a surface, forming air bubbles (by activating some vesicant or injecting gas into the liquid desiccant) and curing the liquid desiccant. The porous desiccant comprises solidified hardening glue having bubbles and lots of desiccant particles or powder distributed evenly therein. Some residual vesicant may remain inside the solidified hardening glue after activation. The bubbles inside the porous desiccant enhance the absorption rate and efficiency of the desiccant so that moisture and gaseous oxygen inside the OLED package can be absorbed rapidly.
    Type: Application
    Filed: April 15, 2003
    Publication date: April 29, 2004
    Inventors: Tung-Sheng Cheng, Yu-Kai Han, Yen-Hua Lin, Pei-Chuan Yeh, Hsia-Tsai Hsiao, Jerry Yen, Chia-Liang Peng, Yi-Fan Su
  • Publication number: 20030230973
    Abstract: The present invention provides an organic electro-luminescence device and fabricating thereof. The organic electro-luminescence device comprises a substrate, an anode on said substrate, a light-emitting layer on said anode, a cathode on said light-emitting layer, and an ion-doping layer between said cathode and said light-emitting layer, wherein said ion doping layer is Alq3 doped.
    Type: Application
    Filed: June 12, 2003
    Publication date: December 18, 2003
    Inventors: twTung-Sheng Cheng, tYu-Kai Han, Chien-Ming Chen, Jerry Yen
  • Publication number: 20030162400
    Abstract: A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic circuit region of the semiconductor device, the deep trench isolation being filled with an insulative material. The deep trench isolation thereby prevents the propagation of crystal defects generated in the logic circuit region from propagating into the memory storage region.
    Type: Application
    Filed: February 22, 2002
    Publication date: August 28, 2003
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tze-Chiang Chen, Liang-Kai Han
  • Publication number: 20030094660
    Abstract: A semiconductor structure having silicon dioxide layers of different thicknesses is fabricated by forming a sacrificial silicon dioxide layer on the surface of a substrate; implanting nitrogen ions through the sacrificial silicon dioxide layer into first areas of the semiconductor substrate; implanting chlorine and/or bromine ions through the sacrificial silicon dioxide layer into second areas of the semiconductor substrate where silicon dioxide having the highest thickness is to be formed; removing the sacrificial silicon dioxide layer; and then growing a layer of silicon dioxide on the surface of the semiconductor substrate. The growth rate of the silicon dioxide will be faster in the areas containing the chlorine and/or bromine ions and therefore the silicon dioxide layer will be thicker in those regions as compared to the silicon dioxide layer in the regions not containing the chlorine and/or bromine ions.
    Type: Application
    Filed: October 3, 2001
    Publication date: May 22, 2003
    Inventors: Scott W. Crowder, Anthony Gene Domenicucci, Liang-Kai Han, Michael John Hargrove, Paul Andrew Ronsheim
  • Publication number: 20030033315
    Abstract: The invention relates to a method for administrating a data base comprising a document set, a schema and a repository. The data base comprises a structure index, into which a document reference and, assigned to said document reference, at least one structure path reference of the referenced document is mappable as supplementary path reference. Further at least one schema path reference is mappable into the structure index as missing path reference. The invention relates to a data base. The data base is installed for administration by the inventive administration method. The invention relates to a computer system with a storage unit and a central processing unit. The storage unit of the computer system includes a data base, which is administrated according to the invention by means of the central processing unit.
    Type: Application
    Filed: July 10, 2002
    Publication date: February 13, 2003
    Inventor: Kay Hans-Peter Winkler
  • Patent number: 6410402
    Abstract: Disclosed is a method of providing variant fills in a semiconductor substrate having a plurality of trenches by providing a semiconductor substrate with a first set of trenches and a second set of trenches, filling all the trenches with a first fill material, masking the second set of trenches in a manner effective in resisting an etching of said first fill material, etching the first fill material in the first set of trenches to a depth effective in permitting the first set of trenches to be plugged, plugging the first set of trenches with a material resistant to an etching of the first fill material, etching the first fill material from the second set of trenches; and then filling the second set of trenches with a second fill material. The process may be generalized to more than two fill materials.
    Type: Grant
    Filed: October 5, 2000
    Date of Patent: June 25, 2002
    Assignee: International Business Machines Corporation
    Inventors: Jay Harrington, Liang-Kai Han
  • Patent number: 6369434
    Abstract: A p-type MOSFET having very shallow p-junction extensions. The semiconductor device is produced on a substrate by creating a layer of implanted nitrogen ions extending from the substrate surface to a predetermined depth preferably less than about 800 Å. The gate electrode serves as a mask so that the nitrogen implantation does not filly extend under the gate electrode. Boron is also implanted to an extent and depth comparable to the nitrogen implantation thereby forming very shallow p-junction extensions that remain confined substantially within the nitrogen layer even after thermal treatment. There is thus produced a pMOSFET having very shallow p-junction extensions in a containment layer of nitrogen and boron in the semiconductor material.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: April 9, 2002
    Assignee: International Business Machines Corporation
    Inventors: Kai Chen, Scott W. Crowder, Liang-Kai Han, Michael J. Hargrove, Kam-Leung Lee, Hung Y. Ng
  • Patent number: 6335262
    Abstract: A semiconductor structure having silicon dioxide layers of different thicknesses is fabricated by forming a sacrificial silicon dioxide layer on the surface of a substrate; implanting nitrogen ions through the sacrificial silicon dioxide layer into first areas of the semiconductor substrate; implanting chlorine and/or bromine ions through the sacrificial silicon dioxide layer into second areas of the semiconductor substrate where silicon dioxide having the highest thickness is to be formed; removing the sacrificial silicon dioxide layer; and then growing a layer of silicon dioxide on the surface of the semiconductor substrate. The growth rate of the silicon dioxide will be faster in the areas containing the chlorine and/or bromine ions and therefore the silicon dioxide layer will be thicker in those regions as compared to the silicon dioxide layer in the regions not containing the chlorine and/or bromine ions.
    Type: Grant
    Filed: January 14, 1999
    Date of Patent: January 1, 2002
    Assignee: International Business Machines Corporation
    Inventors: Scott W. Crowder, Anthony Gene Domenicucci, Liang-Kai Han, Michael John Hargrove, Paul Andrew Ronsheim
  • Patent number: 6297127
    Abstract: Shallow trench isolation is combined with optional deep trenches that are self-aligned with the shallow trenches, at the corners of the shallow trenches, and have a deep trench width that is controlled by the thickness of a temporary sidewall deposited in the interior of the shallow trench and is limited by the sidewall deposition thickness of the deep trench fill.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: October 2, 2001
    Assignee: International Business Machines Corporation
    Inventors: Bomy A. Chen, Liang-Kai Han, Robert Hannon, Jay G. Harrington, Herbert L. Ho, Hsing-Jen Wann
  • Patent number: 6258673
    Abstract: A method of forming an integrated circuit having four thicknesses of gate oxide in four sets of active areas by: oxidizing the silicon substrate to form an initial oxide having a thickness appropriate for a desired threshold voltage transistor; depositing a blocking mask to leave a first and fourth set of active areas exposed; implanting the first and fourth set of active areas with a dose of growth-altering ions, thereby making the first set of active areas more or less resistant to oxidation and simultaneously making the fourth set of active areas susceptible to accelerated oxidation; stripping the blocking mask; forming a second blocking mask to leave the first and second sets of active areas exposed; stripping the initial oxide in exposed active areas; stripping the second blocking mask; surface cleaning the wafer; and oxidizing the substrate in a second oxidation step such that a standard oxide thickness is formed in the second set of active areas, whereby an oxide thickness of more or less than the stan
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: July 10, 2001
    Assignee: International Business Machines Corporation
    Inventors: Kevin M. Houlihan, Liang-Kai Han, Dale W. Martin