Abstract: A method to implement a fixed-point scale layer in a neural network for data processing is provided in the present disclosure. The method includes: receiving fixed-point input data over a channel of a standalone floating-point scale layer, and converting the floating-point input data into fixed-point input data of the standalone floating-point scale layer; obtaining fixed-point quantization parameters in each channel based on the input data and floating-point parameters ?i, ?i in each channel; converting the standalone floating-point scale layer based on the fixed-point quantization parameters into a fixed-point scale layer for processing the fixed-point input data to generate fixed-point output data; and mapping the fixed-point scale layer to a fixed-point convolution layer and the computation of convolution is done by matrix multiplication that can be executed on a GEMM engine.

Abstract: A method including: providing a design data of an integrated circuit (IC), the design data comprising a first cell; identifying a first conductive line in the first cell as a critical internal net of the first cell, wherein the first conductive line is electrically connected between an input terminal of the first cell and an output terminal of the first cell; providing a library of the first cell, wherein the library includes a table of timing or power parameters of the first cell based on a multidimensional input set associated with the critical internal net; updating the design data by determining a timing or power value of the first cell based on the table; performing a timing analysis on the updated design data; and forming a photomask based on the updated design data.

Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in a group of cut patterns which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region; forming a base on the HV region and fin-shaped structures on the LV region; forming a first insulating around the fin-shaped structures; removing the base, the first insulating layer, and part of the fin-shaped structures to form a first trench in the HV region and a second trench in the LV region; forming a second insulating layer in the first trench and the second trench; and planarizing the second insulating layer to form a first shallow trench isolation (STI) on the HV region and a second STI on the LV region.

Abstract: In some embodiments, a process can include obtaining a first formation fluid sample using a sample-line of a focused fluid sampling system and obtaining a second formation fluid sample using a guard-line of the focused fluid sampling system. The process can also include measuring a first optical density spectrum of the first formation fluid sample and measuring a second optical density spectrum of the second formation fluid sample. The process can also include decolorizing the first and second optical density spectrums to produce a decolorized first spectrum and a decolorized second spectrum, respectively. The process can also include normalizing the first and second decolorized spectrums to provide a first normalized spectrum and a second normalized spectrum. The process can also include determining a difference between the first and the second normalized spectrums to provide a sampling difference and adjusting a fluid sampling operation based on the sampling difference.

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.

Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.

Abstract: A power converter improving input overvoltage from output voltage drop is provided. The power converter includes a high-side switch, a low-side switch, a control circuit, a voltage threshold determining circuit and a voltage drop suppression circuit. The voltage threshold determining circuit determines whether or not an output voltage of the power converter is dropping to determine or adjust a voltage threshold. The voltage drop suppression circuit detects a voltage of a first terminal of the high-side switch. When the voltage drop suppression circuit determines that the detected voltage of the first terminal of the high-side switch is higher than the voltage threshold, the voltage drop suppression circuit pulls down the voltage of the first terminal of the high-side switch.

Abstract: An open-loop inductor current emulating circuit is provided. A current sensor circuit senses a current flowing through a first terminal of a low-side switch to output a current sensed signal. An emulation controller circuit outputs a plurality of charging current signals according to currents of a plurality of rising waveforms of the current sensed signal. The emulation controller circuit outputs a plurality of discharging current signals according to currents of a plurality of falling waveforms of the current sensed signal. A charging and discharging circuit generates a plurality of charging currents according to the charging current signals, and generates a plurality of discharging currents according to the discharging current signals. The charging and discharging circuit alternatively outputs the charging currents and the discharging currents to the capacitor to charge and discharge the capacitor multiple times, thereby achieving a purpose of emulating an inductor current.

Abstract: Provided is a terminal including one or more processors and memory storing one or more computer programs configured to be executed by the one or more processors. The one or more computer programs including instructions for: displaying an edit screen on a display, the edit screen including a first area that displays a video obtained by playing back an archive of a live-stream associated with a plurality of selling items, an object that indicates a current playback position of the video, and a second area that selectably displays the plurality of selling items associated with the live-stream; and communicating with a server over a network so that a result of edits made through the edit screen is associated with a selling item selected in the second area.

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

Abstract: Systems, methods, and computer-readable media are disclosed for determining virtual product placement opportunities in a media content and determining product candidates for virtual insertion into the media content. The product placement system may determine shot segments from the media content and for each shot segment may determine candidate product placement locations. The product placement system may determine contextual information from the shot segments and from the contextual information determine candidate products suitable for the product placement locations. The product placement system may determine total screen time for each product placement opportunity as well as quality of each opportunity. For each product and product placement opportunity, the product placement system may determine an expected revenue and a projected insertion cost.

Abstract: Interaction is created between users and streamers even when the users give gifts to the streamers outside live-streams. Provided is a terminal of a user, which includes: one or more processors; and memory storing one or more computer programs configured to be executed by the one or more processors. The one or more computer programs include instructions for: receiving, from the user, an instruction to use a gift for a streamer while the user is not participating in a live-stream of the streamer; and causing an output unit to output an effect corresponding to the use of the gift by the user while the streamer is live-streaming.

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.

Abstract: A system (for generating a layout diagram of a wire routing arrangement) includes a processor and memory including computer program code for one or more programs, the system generating the layout diagram including: placing, relative to a given one of masks in a multi-patterning context, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining that the first candidate location results in an intra-row non-circular group of a given row which violates a design rule, the intra-row non-circular group including first and second cut patterns which abut a same boundary of the given row, and a total number of cut patterns in the being an even number; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Abstract: A layout method and a semiconductor device are disclosed. The layout method includes: generating a design layout by placing a cell, wherein the cell includes: a first conductive segment overlapping a source/drain region and disposed immediately adjacent to a first power rail, wherein the first conductive segment has a length substantially equal to a cell length; a second conductive segment; and a third conductive segment between the first and second conductive segments. The layout method further includes: providing a fourth conductive segment and a fifth conductive segment to the design layout, wherein the fourth and fifth conductive segments are aligned in a first direction.

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

Abstract: An antenna structure and an electronic device are provided. The electronic device includes a housing and an antenna structure disposed in the housing. The antenna structure includes a carrier having a first carrying part and a second carrying part connected to each other, a switching circuit, a first radiating element, and a second radiating element. A thickness of the first carrying part is greater than a thickness of the second carrying part. The second carrying part includes a circuit layer and a ground layer respectively formed on opposite surfaces of the second carrying part. The switching circuit is located on the circuit layer. The first radiating element and the second radiating element are disposed on the carrier and respectively electrically connected to a feed element and the switching circuit. The second radiating element and the first radiating element are apart from and couple with each other.