Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.

Abstract: An optical module includes a micro spectrometer. The micro spectrometer includes an optical crystal, a lens, and a photosensitive assembly. The optical crystal is configured to receive detection light and covert the detection light into interference light. The optical crystal is surrounded by a sleeve, the sleeve configured to fix a position of the optical crystal. The lens is configured for receiving the interference light and focusing the interference light. The photosensitive assembly is configured for imaging the interference light into an interference image. The optical module further comprises a controller. The controller is electrically connected to the photosensitive assembly, and the controller is used to convert the interference image into light wavelength signals and light intensity signals.

Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.

Abstract: The high-density MRAM device of the present invention has a second interlayer dielectric (ILD) layer covering the capping layer in the MRAM cell array area and the logic area. The thickness of the second ILD layer in the MRAM cell array area is greater than that in the logic area. The composition of the second ILD layer in the logic area is different from the composition of the second ILD layer in the MRAM cell array area.

Abstract: Provided is a terminal including one or more processors and memory storing one or more computer programs configured to be executed by the one or more processors. The one or more computer programs including instructions for: displaying an edit screen on a display, the edit screen including a first area that displays a video obtained by playing back an archive of a live-stream associated with a plurality of selling items, an object that indicates a current playback position of the video, and a second area that selectably displays the plurality of selling items associated with the live-stream; and communicating with a server over a network so that a result of edits made through the edit screen is associated with a selling item selected in the second area.

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.

Abstract: This invention relates to a latch for selectively binding lower and upper portions of a container. The latch includes a base having a front face, a rear face, a connected end, and a selectively engageable binding end. The rear face further includes an upward hook, a downward hook, and a binding tooth. The latch is characterized in that the upward hook and the downward hook are configured to engage the lower portion of the container and permit both axial and pivotal movement of latch. The axial movement is between an upward position and a low profile position The pivotal movement is about the connected end such that binding end can move between a disengaged and an engaged position.

Abstract: Quantized softmax layers in neural networks are described. Some embodiments involve receiving, at an input to a softmax layer of a neural network from an intermediate layer of the neural network, a non-normalized output comprising a plurality of intermediate network decision values. Then for each intermediate network decision value of the plurality of intermediate network decision values, the embodiment involves: calculating a difference between the intermediate network decision value and a maximum network decision value; requesting, from a lookup table, a corresponding lookup table value using the difference between the intermediate network decision value and the maximum network decision value; and selecting the corresponding lookup table value as a corresponding decision value. A normalized output is then generated comprising the corresponding lookup table value for said each intermediate network decision value of the plurality of intermediate network decision values.

Abstract: Various embodiments provide for quantizing a trained neural network with removal of normalization with respect to at least one layer of the quantized neural network, such as a quantized multiple fan-in layer (e.g., element-wise add or sum layer).

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

Abstract: A siphon pipe applied to a container unit for hydroponics comprising a pipe which is an integrated molded U-shaped body, the pipe having a U-section and two straight sections, the U-section having a continuously varying cross-sectional profile with a long axial length which gradually increases from one end toward the top, and then gradually decreases from the top toward the other end, thereby forming a continuously varying cross-sectional profile of the U-section. When the water level in the container unit rises to the U-section of the siphon pipe, the water level in the siphon pipe rises rapidly and flows to the outlet of the siphon pipe, and at the same time the air inside the pipe is brought out, to achieve a high-efficiency siphoning effect.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to and directly contacting the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is a single layer structure made of dielectric material and an edge of the cap layer contacts the first IMD layer directly.

Abstract: A method includes forming a circuit region over a substrate. The circuit region includes at least one active region extending along a first direction, and at least one gate region extending across the at least one active region and along a second direction transverse to the first direction. At least one first input/output (TO) pattern and at least one second TO pattern are correspondingly formed in different first and second metal layers to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first TO pattern extends along a third direction oblique to both the first direction and the second direction. The at least one second TO pattern extends along a fourth direction oblique to both the first direction and the second direction, the fourth direction transverse to the third direction.

Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in a group of cut patterns which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Abstract: A system (for generating a layout diagram of a wire routing arrangement) includes a processor and memory including computer program code for one or more programs, the system generating the layout diagram including: placing, relative to a given one of masks in a multi-patterning context, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining that the first candidate location results in an intra-row non-circular group of a given row which violates a design rule, the intra-row non-circular group including first and second cut patterns which abut a same boundary of the given row, and a total number of cut patterns in the being an even number; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Abstract: Interaction is created between users and streamers even when the users give gifts to the streamers outside live-streams. Provided is a terminal of a user, which includes: one or more processors; and memory storing one or more computer programs configured to be executed by the one or more processors. The one or more computer programs include instructions for: receiving, from the user, an instruction to use a gift for a streamer while the user is not participating in a live-stream of the streamer; and causing an output unit to output an effect corresponding to the use of the gift by the user while the streamer is live-streaming.

Abstract: A method includes clustering cells in a group of cells into a selected number of clusters, and ranking the clusters based on a list of prioritized features to generate a list of ranked clusters. The method also includes ranking cells in each of one or more ranked clusters in the list of ranked clusters, based on the list of prioritized features, to generate a list of ranked critical cells. The method further includes outputting the list of ranked critical cells for use in adjusting cell layouts based on the ranked critical cells.

Abstract: A switching charger for supplying stable power is provided. First input terminals of first and fourth operational amplifiers and a second input terminal of a second operational amplifier are connected to a battery. A second input terminal of the first operational amplifier is coupled to a reference voltage. A first input terminal of the second operational amplifier and a second input terminal of the fourth operational amplifier are connected to an inductor. A first input terminal of a third operational amplifier is connected to an input power source. A second input terminal of the third operational amplifier is connected to a system circuit. A first selector circuit is connected to output terminals of the third and fourth operational amplifiers. A second selector circuit is connected to output terminals of the first and second operational amplifiers and the first selector circuit.