Abstract: A semiconductor device includes a substrate, a first transistor, a second transistor and a third transistor. The substrate includes a high-voltage (HV) area, a medium-voltage (MV) area, and a low-voltage (LV) area. The first transistor is disposed in the HV area and includes a first gate dielectric layer and a first gate electrode. The second transistor is disposed in the LV area and includes a plurality of fin-shaped structures and a second gate electrode. The third transistor is disposed in the MV area and includes a third gate dielectric layer and a third gate electrode. The topmost surfaces of the first gate electrode, the second gate electrode and the third gate electrode are coplanar with each other.

Abstract: The disclosure discloses a structure of high-voltage (HV) transistor which includes a substrate. An epitaxial doped structure with a first conductive type is formed in the substrate, wherein a top portion of the epitaxial doped structure includes a top undoped epitaxial layer. A gate structure is disposed on the substrate and at least overlapping with the top undoped epitaxial layer. A source/drain (S/D) region with a second conductive type is formed in the epitaxial doped structure at a side of the gate structure. The first conductive type is different from the second conductive type.

Abstract: A high voltage transistor structure including a substrate, a first drift region, a second drift region, a first cap layer, a second cap layer, a gate structure, a first source and drain region, and a second source and drain region is provided. The first and second drift regions are disposed in the substrate. The first and second cap layers are respectively disposed on the first and second drift regions. The gate structure is disposed on the substrate and located over at least a portion of the first drift region and at least a portion of the second drift region. The first and second source and drain regions are respectively disposed in the first and second drift regions and located on two sides of the gate structure. The size of the first drift region and the size of the second drift region are asymmetric.

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

Abstract: The present invention provides a second use of mitochondria, which can cure a tendon injury-related disease and prevent a disease caused by a tendon injury. Specifically, the mitochondria disclosed in the present invention have the effect of repairing injured tendon cells and accelerating the healing of the tendon cells. Therefore, by administering a predetermined amount of mitochondria or a composition containing a predetermined amount of mitochondria to a part with a tendon injury, wound healing of the part with the tendon injury can be promoted, thus achieving the effect of repairing the injured tendon and further preventing a joint disease caused by the tendon injury or inflammation.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack for forming a first MTJ; forming a first inter-metal dielectric (IMD) layer around the first MTJ; and performing a second patterning process to remove the first MTJ for forming a second MTJ and a third MTJ.

Abstract: A resistive random access memory (RRAM) structure includes a substrate. A transistor is disposed on the substrate. The transistor includes a gate structure, a source and a drain. A drain contact plug contacts the drain. A metal interlayer dielectric layer is disposed on the drain contact plug. An RRAM is disposed on the drain and within a first trench in the metal interlayer dielectric layer. The RRAM includes the drain contact plug, a metal oxide layer and a top electrode. The drain contact plug serves as a bottom electrode of the RRAM. The metal oxide layer contacts the drain contact plug. The top electrode contacts the metal oxide layer and a metal layer is disposed within the first trench.

Abstract: A silicon photonics optical transceiver device includes a silicon photonics optical module and a heat conducting housing that accommodates the silicon photonic optical module therein. The heat conducting housing has an inner surface formed with a first heat dissipation portion that wraps around and is in contact with transmitter optical sub-assemblies of the silicon photonics optical module to realize thermal conduction, and a second heat dissipation portion that is in contact with a digital signal processor of the silicon photonics optical module to realize thermal conduction.

Abstract: The display system comprising a main control module and a display module is provided. The main control module comprises a display driving circuit and a timing control circuit. The display driving circuit is used to output a display driving signal. The timing control circuit is coupled to the display driving circuit to receive the display driving signal, and convert the display driving signal into a digital signal. The display module comprises a first display panel to an N-th display panel, coupled to the timing control circuit and receiving the digital signal, so as to display corresponding multimedia content according to the digital signal, wherein N is a positive integer greater than 1, and the main control module is independently coupled to the display module.

Abstract: The embodiments according to the present disclosure provide a protective solution, a kit, and a method for isolating mitochondria. The kit includes an extraction tube, a protective solution, and a suction needle. The extraction tube is used to contain cells. The protective solution is used to mix with the cells in the extraction tube to form a mixture solution, and the osmolarity of the protective solution is greater than 0 and less than or equal to 220 mOsm/L. The suction needle is used to suck the mixed solution back and forth to facilitate the release of mitochondria from cells. This method and the protective solution may isolate mitochondria from cells with high efficiency in a simple and convenient way, and the isolated mitochondria have excellent good function.

Abstract: A structure of semiconductor device is provided, including a substrate. First and second trench isolations are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A first germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A second Ge doped layer region is in the portion of the substrate, overlapping with the first Ge doped layer region to form a Ge gradient from high to low along a depth direction under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the first germanium doped layer region.

Abstract: Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes a substrate having a pillar protruding from a surface of the substrate, a gate surrounding a part of a side surface of the pillar, a gate dielectric layer, a first electrode, a second electrode, a variable resistance layer, a first doped region and a second doped region. The gate dielectric layer is disposed between the gate and the pillar. The first electrode is disposed on a top surface of the pillar. The second electrode is disposed on the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The first doped region is disposed in the pillar below the gate and in a part of the substrate below the pillar. The second doped region is disposed in the pillar between the gate and the first electrode.

Abstract: A resistive random access memory (RRAM) structure includes a substrate. A transistor is disposed on the substrate. The transistor includes a gate structure, a source and a drain. A drain contact plug contacts the drain. A metal interlayer dielectric layer is disposed on the drain contact plug. An RRAM is disposed on the drain and within a first trench in the metal interlayer dielectric layer. The RRAM includes the drain contact plug, a metal oxide layer and a top electrode. The drain contact plug serves as a bottom electrode of the RRAM. The metal oxide layer contacts the drain contact plug. The top electrode contacts the metal oxide layer and a metal layer is disposed within the first trench.

Abstract: The present invention discloses a use of a mitochondrial extract to treat and/or prevent a kidney injury-related disease. Specifically, by administering the mitochondrial extract disclosed in the present invention to a patient having a kidney injury-related disease, the kidney injury-related disease can be effectively alleviated and prevented from deterioration.

Abstract: A system may comprise a printed circuit board (PCB) including a top surface, and a bracket including a top surface configured to receive and couple to a key switch and a bottom surface including at least two protrusions that extend normal to the bottom surface of the bracket. The bracket can be configured to mount to the PCB such that the bottom surface of the bracket is coupled to the top surface of the PCB, and the at least two protrusions may each include conductive leads that couple to the top surface of the PCB. The bracket is configured to only cover a portion of a bottom surface of the key switch when coupled to the key switch. An LED can be mounted to the top surface of the PCB, laterally adjacent to the bracket, and under the key switch at a location not covered by the bracket.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.

Abstract: Provided is a semiconductor device, including a substrate including a pixel region, a gate structure on the substrate in the pixel region, wherein the gate structure comprises a gate dielectric layer and a gate conductive layer on the gate dielectric layer; a dielectric layer located over the substrate and the gate structure; and a contact located in the dielectric layer and electrically connected to the gate conductive layer. The contact includes a doped polysilicon layer in contact with the gate conductive layer; a metal layer located on the doped polysilicon layer, wherein a part of the metal layer is embedded in the doped polysilicon layer; a barrier layer located between the metal layer and the doped polysilicon layer; and a metal silicide layer located between the barrier layer and the doped polysilicon layer.

Abstract: Aspects of the present disclosure address systems and methods for fixed-point quantization using a dynamic quantization level adjustment scheme. Consistent with some embodiments, a method comprises accessing a neural network comprising floating-point representations of filter weights corresponding to one or more convolution layers. The method further includes determining a peak value of interest from the filter weights and determining a quantization level for the filter weights based on a number of bits in a quantization scheme. The method further includes dynamically adjusting the quantization level based on one or more constraints. The method further includes determining a quantization scale of the filter weights based on the peak value of interest and the adjusted quantization level. The method further includes quantizing the floating-point representations of the filter weights using the quantization scale to generate fixed-point representations of the filter weights.

Abstract: A semiconductor device includes a first metal interconnection on a substrate, a first inter-metal dielectric (IMD) layer around the first metal interconnection, an electromigration enhancing layer on the first metal interconnection, a second IMD layer on and around the electromigration enhancing layer, and a second metal interconnection on the electromigration enhancing layer.

Abstract: A method and an apparatus for video processing are provided. The method includes that a decoding terminal receives a plurality of coded video frames coded using one or more generative adversarial networks (GANs), receives network parameters related to the one or more GANs, and decodes the plurality of coded video frames using GANs based on the network parameters. Further, the one or more GANs respectively implement one or more video coding functions including reference-frame coding, motion-compensated frame prediction, and residue-frame coding.