Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The method may include forming a first hardmask layer over a substrate. The method may include forming a second hardmask layer over the first hardmask layer. The method may include transferring a pattern from the second hardmask layer to the first hardmask layer, wherein the pattern in the first hardmask layer comprises a plurality of protruding structures, and each of the plurality of protruding structures has respective portions of its two sidewalls extending toward each other. The method may include depositing a modification layer extending along at least the respective portions of the sidewalls of each of the protruding structures. The method may include etching the substrate with the protruding structures and the modification layer both serving as a mask.

Abstract: A method of processing a substrate includes exposing the substrate to a boron-containing precursor to adsorb over the substrate, where the substrate includes a dielectric layer formed over a conductive layer, and the conductive layer is exposed at a bottom of a recess formed in the dielectric layer. The method includes exposing the adsorbed boron-containing precursor to a plasma and filling the recess with a conductive fill material bottom up by a vapor deposition process, where a vertical deposition rate of the conductive fill material is greater than a lateral deposition rate of the conductive fill material.

Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, forming a nucleation enhancement layer on a sidewall of the first layer in the recessed feature and depositing a metal layer in the recessed feature by vapor phase deposition, where the metal layer is deposited on the second layer and on the nucleation enhancement layer. An initial metal layer may be selectively formed on the second layer in the recessed feature before forming the nucleation enhancement layer.

Abstract: A method for forming a semiconductor device can include providing a substrate including a via in a dielectric layer, forming a ruthenium metal plug in the via, and at least part of the ruthenium metal plug can be formed directly on the dielectric layer in the via, forming a metal cap layer directly on the ruthenium metal plug, and forming a metallization layer, such as a copper-containing trench, over the ruthenium metal plug, such that the metal cap layer is between the metallization layer and the ruthenium metal plug, which can prevent intermixing of the ruthenium of the ruthenium metal plug with the metal or metals in the metallization layer.

Abstract: Aspects of the present disclosure provide a method for fabricating a forksheet semiconductor structure. For example, the method can include forming on a substrate a multi-layer stack including first and second semiconductor layers stacked over one another alternately, forming a cap layer over the multi-layer stack, forming a mandrel structure from the multi-layer stack and the cap layer, forming a fill material that surrounds the mandrel structure and has a top surface level with a top of the mandrel structure, partially recessing the cap layer to uncover opposite inner sidewalls of the fill material, forming sidewall spacers on the opposite inner sidewalls, directionally etching the multi-layer stack to define an insulation wall trench using the sidewall spacers as an etch mask, and forming an insulation material within the insulation wall trench to form an insulation wall that separates the multi-layer stack into insulated first and second multi-layer stacks.

Abstract: A method for processing a substrate that includes: treating the substrate with a halogen-containing catalyst, the substrate including a semiconductor layer, a dielectric layer disposed over the semiconductor layer, a recess formed in the dielectric layer, and a layer of a first metal disposed between the dielectric layer and the semiconductor layer, the layer of the first metal being at a bottom of the recess, the halogen-containing catalyst modifying a surface of the layer of the first metal; after treating the substrate with the halogen-containing catalyst, treating the substrate with a molecular inhibitor (MI), the MI covering sidewalls of the dielectric layer in the recess; depositing a second metal over the modified surface of the layer of the first metal in the recess, where the MI covering the sidewalls prevents deposition of the second metal on the dielectric layer.

Abstract: A method for processing a substrate that includes: depositing a filling material over the substrate including a first recess and a second recess, the filling material filling the first recess and the second recess; patterning the filling material such that the first recess is reopened while the second recess remains filled with the filling material; filling the first recess with a conductive material to a first height; etching the filling material selectively to the conductive material to reopen the second recess; filling a remainder of the first recess and the second recess with the conductive material; and performing an etch back process to etch the conductive material such that the first recess and the second recess are filled with the conductive material to a second height.

Abstract: Embodiments of methods are provided for thermal dry etching of a ruthenium (Ru) metal layer. In the disclosed embodiments, a substrate containing a Ru metal layer formed thereon is exposed to a gas pulse sequence, while the substrate is held at a relatively high substrate temperature (e.g., a temperature greater than or equal to about 160° C.), to provide thermal etching of the Ru metal layer. As described further herein, the gas pulse sequence may generally include a plurality of gas pulses, which are supplied to the substrate sequentially with substantially no overlap between gas pulses. The gas pulses supplied to the substrate form: (i) volatile reaction products that are vaporized from the Ru surface, and (ii) non-volatile oxide surface layers that are removed from the Ru surface by the next gas pulse, resulting in atomic layer etching (ALE) of the Ru metal layer.

Abstract: A method of patterning a substrate includes forming a first line, a second line, and a third line over the substrate, the first line, the second line, and the third line being parallel in a plan view, and forming a fourth line and a fifth line over the first line, the second line, and the third line, the fourth line and the fifth line being orthogonal to the first line in the plan view. The method further includes etching a hole through the second line using the first line, the third line, the fourth line, and the fifth line as an etching mask, and filling the hole with a dielectric material to form a block.

Abstract: Improved process flows and methods are provided for processing a semiconductor substrate have exposed dielectric and metal-containing surfaces. More specifically, improved process flows and methods are provided for pre-cleaning the metal-containing surfaces prior to depositing a metal material onto the metal-containing surfaces. Hot vapor-phase etching is used to remove a native oxide film from the metal-containing surfaces. Prior to hot vapor-phase etching, the semiconductor substrate is exposed to a first silicon-containing gas to deposit an inhibitor film onto the exposed dielectric and metal-containing surfaces. The inhibitor film protects the dielectric surfaces while the native oxide film is being removed via the hot vapor-phase etching. In some embodiments, the semiconductor substrate is exposed to a second silicon-containing gas, after hot vapor-phase etching, to remove residues of the hot vapor-phase etching process from the pre-cleaned metal-containing surfaces.

Abstract: Various embodiments of stacked structures, process steps and methods are provided herein for etching high aspect ratio features (e.g., contact holes, vias, trenches, etc.) within a stacked structure comprising a hard mask layer, which is formed above and in contact with one or more underlying layers. At least one etch stop layer (ESL) is provided within the hard mask layer to divide the hard mask layer into two or more distinct portions. When the stacked structure is subsequently etched to form high aspect ratio features within the hard mask layer, such as contact holes or vias that extend through the hard mask layer, the ESL(s) included within the hard mask layer improve etch rate and critical dimension (CD) uniformity of the features etched within the hard mask layer.

Abstract: A method of fabricating an amorphous carbon layer (ACL) mask includes forming an ACL on an underlying layer. The ACL includes a soft ACL portion that has a first hardness and a hard ACL portion that has a second hardness. The soft ACL portion underlies the hard ACL portion. The second hardness is greater than the first hardness. The method further includes forming a patterned layer over the ACL and forming an ACL mask by etching through both the soft ACL portion and the hard ACL portion of the ACL to expose the underlying layer using the patterned layer as an etch mask. Forming the ACL may include depositing one or both of the soft ACL portion and the hard ACL portion. Processing conditions may also be varied while forming the ACL to create a hardness gradient that transitions from softer to harder.

Abstract: A method for processing a substrate includes treating the substrate with a small molecular inhibitor (SMI), the substrate including a recess formed in a dielectric layer and a first metal layer in the recess, the SMI covering a surface of the first metal layer. The method further includes, after treating the substrate with the SMI, treating the substrate with a large molecular inhibitor (LMI), the LMI covering sidewalls of the dielectric layer in the recess. The method further includes heating the substrate to remove the SMI from the first metal layer and to expose the first metal layer in the recess, where the LMI remains on the sidewalls after removing the SMI from the first metal layer. The method further includes depositing a second metal over the first metal layer in the recess, where the LMI covering the sidewalls prevents deposition of the second metal on the dielectric layer.

Abstract: A method of processing substrates, in one example microelectronic workpieces, is disclosed that includes forming a multi-layer metal hard mask (MHM) layer in which at least one lower layer of the multi-layer MHM is comprised of ruthenium (Ru). The Ru MHM layer may be an atomic layer deposition (ALD) Ru MHM layer formed over one or more underlying layers on a substrate. The ALD Ru MHM layer may be etched to provide a patterned ALD Ru MHM layer, and then the one or more underlying layers may be etched using, at least in part, the patterned ALD Ru MHM layer as a mask to protect portion of the one or more underlying layers. In one embodiment, at least one of the underlying layers is a hard mask layer.

Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.

Abstract: A method of preparing a self-aligned via on a semiconductor workpiece includes using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules. The integrated sequence of processing steps include receiving the workpiece into the common manufacturing platform, the workpiece having a pattern of metal features in a dielectric layer wherein exposed surfaces of the metal features and exposed surfaces of the dielectric layer together define an upper planar surface; selectively etching the metal features to form a recess pattern by recessing the exposed surfaces of the metal features beneath the exposed surfaces of the dielectric layer using one of the one or more etching modules; and depositing an etch stop layer over the recess pattern using one of the one or more film-forming modules.

Abstract: Methods and systems for selective deposition of conductive a cap for FAV features are described. In an embodiment, a method may include receiving a substrate having an interlayer dielectrics (ILD) layer, the ILD layer having a recess, the recess having a conductive layer formed therein, the conductive layer comprising a first conductive material. Additionally, such a method may include forming a cap within a region defined by the recess and in contact with a surface of the conductive layer, the cap comprising a second conductive material. The method may also include forming a conformal etch stop layer in contact with a surface of the cap and in contact with a region of the ILD layer. Further, the method may include selectively etching the etch stop layer using a plasma etch process, wherein the plasma etch process removes the etch stop layer selective to the second conductive material comprising the cap.

Abstract: A method including providing a substrate including metal gate stacks and source/drain contact regions in alternating arrangement along a surface of the substrate, each of the source/drain contact regions being recessed within a respective opening between adjacent metal gate stacks such that source/drain contact regions provide a bottom of the opening and adjacent metal gate stacks provide sidewalls, and a dielectric covering the substrate such that the dielectric fills each opening. The substrate is exposed to an initial plasma etch process to remove a first portion of the dielectric from each opening down to a first depth, and a sacrificial gate capping layer is formed on the substrate while leaving each of the openings uncovered. The substrate is exposed to another plasma etch process to remove the sacrificial gate capping layer while removing a second portion of the dielectric from each opening down to a second depth.

Abstract: A substrate is provided with a patterned layer, such as, a photo resist layer which may exhibit line roughness. The patterned layer may be an EUV photo resist layer utilized in a self-aligned multi-patterning process. A tone inversion process having a tone inversion layer is utilized along with a surface treatment of a sidewall of the tone inversion layer so as to improve line roughness characteristics of the process. More specifically, a tone inversion layer may be patterned and then sidewalls of the tone inversion layer may be treated. A fill material may then be deposited upon the substrate including adjacent the sidewalls of the tone inversion layer. When the tone inversion layer is removed, the roughness of the fill material will be reduced due to the use of the sidewall treatment.

Abstract: A method for forming a fully self-aligned via is provided. A workpiece having a pattern of features in a dielectric layer is received into a common manufacturing platform. Metal caps are deposited on the metal features, and a barrier layer is deposited on the metal caps. A first dielectric layer is added to exposed dielectric material. The barrier layer is removed and an etch stop layer is added on the exposed surfaces of the first dielectric layer and the metal caps. Additional dielectric material is added on top of the etch stop layer, then both the additional dielectric material and a portion of the etch stop layer are etched to form a feature to be filled with metal material. An integrated sequence of processing steps is executed within one or more common manufacturing platforms to provide controlled environments. Transfer modules transfer the workpiece between processing modules within and between controlled environments.