Abstract: A display panel includes a first substrate, a second substrate, a plurality of pixel structures, a plurality of color filter patterns, a plurality of spacers, and a liquid crystal layer. The pixel structures are disposed on the first substrate, and each pixel structure includes a reflective electrode. The color filter patterns respectively overlap the reflective electrodes of the pixel structures. The spacers and the liquid crystal layer are disposed between the first substrate and the second substrate. The pixel structures include a first pixel structure, the spacers include a first spacer, and the color filter patterns include a first color filter pattern. The reflective electrode of the first pixel structure of the pixel structures overlaps the first spacer of the spacers and the first color filter pattern of the color filter patterns, and at least a portion of the first spacer does not overlap the first color filter pattern.

Abstract: Various implementations disclosed herein include devices, systems, and methods that generate floorplans and measurements using a three-dimensional (3D) representation of a physical environment generated based on sensor data.

Abstract: A method and device for determining a safety risk of an elevator system, and a non-transitory computer-readable storage medium storing a computer program for implementing the method. A method for determining a safety risk of an elevator system includes determining the safety risk by generating a feature vector based at least on operational state data of the elevator system, and subsequently determining a probability of a transport object being trapped in a car of the elevator system using a neural network model. The feature vector and the probability are an input variable and an output variable of the neural network model, respectively, and the feature vector includes components corresponding to combinations selected from a plurality of state values of a first category of features. Further, the state values of the first category of features are determined based on the operational state data.

Abstract: The present invention discloses a Self-detection circuit based on power detector, comprising a power detector, a coupler, a phased array transmitting channel 1 and a phased array transmitting channel 2, and the power detector is divided into two working modes of phase test and amplitude test. The problems that the self-test circuit is complex and large in chip area are solved.

Abstract: A display device including a display panel is disclosed. The display panel includes a substrate, multiple scan lines, multiple data lines, multiple pixel structures, a first gate driving circuit, and a second gate driving circuit. The pixel structures are electrically connected to the scan lines and the data lines. Multiple first output stage circuits of the first gate driving circuit disposed in a peripheral area are electrically connected to the scan lines. Multiple second output stage circuits of the second gate driving circuit disposed in the peripheral area are electrically connected to the scan lines. A channel width of a first output transistor of the first output stage circuit is greater than a channel width of a second output transistor of the second output stage circuit.

Abstract: The present disclosure provides a field quantitative analysis method and system of lithium, and relates to the technical field of field quantitative analysis of lithium. The method includes: measuring a laser-induced breakdown spectroscopy of a lithium-containing mineral, to obtain spectral data of the lithium-containing mineral; taking the spectral data as an input, and determining a mineral class of the lithium-containing mineral based on a trained mineral classification model; and taking the spectral data as the input, and determining content of lithium in the lithium-containing mineral based on a calibration curve corresponding to the mineral class.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.

Abstract: Embodiments of the present disclosure disclose a method for social networking based on a virtual image, a system, a storage medium, and a terminal device, and is applied to the field of information processing technologies. A social application interface displayed by a social application system includes an object screening control and a virtual image of each social object. In this way, a first social object related to an online state of a current social user is determined through an operation performed on the object screening control, the object screening control is collapsed, and a virtual image of the first target social object is displayed.

Abstract: This invention discloses a display panel includes a substrate and a sub-pixel. The sub-pixel is disposed on the substrate. The sub-pixel includes a transistor, and the transistor includes a gate, a semiconductor layer, a source, a drain, and a dummy electrode. The gate is disposed on the substrate. The semiconductor layer is disposed on the gate. The source and the drain are disposed on the semiconductor layer, the source is disposed at one end of the semiconductor layer, and the drain is disposed at the other end of the semiconductor layer. The dummy electrode is disposed on the semiconductor layer and between the source and the drain. The dummy electrode and the source are separated, the dummy electrode and the drain are separated, and the dummy electrode is electrically floating.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type; a well region of the first conductivity type in the semiconductor substrate; and a fin disposed on the semiconductor substrate within the well region. The fin extends along a first direction. The fin includes a first portion and a second portion that is contiguous with the first portion. The first portion includes a counter-doping region having dopants of a second conductivity type. A gate extends over the fin along a second direction. The gate overlaps with the first portion of the fin and does not overlap with the second portion of the fin.

Abstract: A MOS capacitor includes a substrate of a first conductivity type including a fin surrounded by an isolation region. The fin protrudes from a top surface of the isolation region. A counter-doping region of a second conductivity type is disposed in the fin and serves as a first electrode plate of the MOS capacitor. A capacitor dielectric layer covers a sidewall and a top surface of the fin. A metal gate covers the capacitor dielectric layer and serves as a second electrode plate of the MOS capacitor.

Abstract: The invention provides a capacitor structure with a fin structure, which comprises a fin structure located on a substrate, a lower electrode layer, a high dielectric constant layer and an upper electrode layer stacked on the fin structure in sequence, and an ion doped region located in the substrate below the fin structure, and a top surface of the ion doped region is aligned with a bottom surface of the fin structure.

Abstract: A display panel including a substrate, scan lines, data lines, pixel structures, and a light shielding pattern layer is provided. The substrate is provided with a display area. The scan lines and the data lines are disposed on the substrate, and intersect with each other. The pixel structures are disposed in the display area, and each includes a display transistor and a pixel electrode. The display transistor includes a first semiconductor pattern, a first gate electrode, a first source electrode, and a first drain electrode. The first gate electrode is disposed between the substrate and the first semiconductor pattern, and is electrically connected to one of the scan lines. The first source electrode is electrically connected to one of the data lines. The pixel electrode is electrically connected to the first drain electrode of the display transistor. The light shielding pattern layer is disposed between the first gate electrode and the substrate, and has a first opening overlapping the first gate electrode.

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.

Abstract: The present application provides a day-ahead scheduling method and apparatus for a power system, an electronic device, and a storage medium, where the method includes: obtaining power system prediction parameters in a to-be-scheduled time period, where the power system prediction parameters include thermal power unit parameters, renewable energy station parameters, load parameters, energy storage station (ESS) parameters, node parameters, a transmission line parameter and other power gird parameters; constructing a day-ahead scheduling optimization model and generating multiple renewable energy power scenarios based on the power system prediction parameters; solving the day-ahead scheduling optimization model to obtain day-ahead scheduling results; verifying the day-ahead scheduling results based on the power system prediction parameters and the multiple renewable energy power scenarios; and in case that the verifying the day-ahead scheduling results successes, outputting the day-ahead scheduling results.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate including a fin portion, first and second doped regions having a first conductive type, first and second contacts, and first and second metal silicide layers. The fin portion protrudes from a surface of the substrate. The first doped region is disposed in the fin portion. The second doped region is disposed in the fin portion and connected to the first doped region. A doping concentration of the second doped region is greater than that of the first doped region. The first contact is disposed on the first doped region. The second contact is disposed on the second doped region. The first metal silicide layer is disposed between the first contact and the first doped region. The second metal silicide layer is disposed between the second contact and the second doped region.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a transistor region and an one time programmable (OTP) capacitor region, forming a first fin-shaped structure on the transistor region and a second fin-shaped structure on the OTP capacitor region, and then performing an oxidation process to form a gate oxide layer on the first fin-shaped structure and the second fin-shaped structure. Preferably, the first fin-shaped structure and the second fin-shaped structure have different shapes under a cross-section perspective.

Abstract: Systems and methods for performing document entity extraction are described herein. The method can include receiving an inference document and a target schema. The method can also include generating one or more document inputs from the inference document and one or more schema inputs from the target schema. The method can further include, for each combination of the document input and schema input, obtaining one or more extraction inputs by generating a respective extraction input based on the combination, providing the respective extraction input to the machine-learned model, and receiving a respective output of the machine-learned model based on the respective extraction. The method can also include validating the extracted entity data based on reference spatial locations and inference spatial locations and outputting the validated extracted entity data.

Abstract: A display panel includes a substrate, multiple scan lines, multiple data lines, and multiple pixel structures. The scan lines and the data lines are disposed on the substrate. The pixel structure is disposed on the substrate and electrically connected to the scan lines and the data lines, and includes an active device, a pixel electrode, a capacitor electrode, an overcoat layer, a first common electrode, a second common electrode, a first passivation layer, and a second passivation layer. The active device is electrically connected one scan line, one data line, and the pixel electrode. The capacitor electrode extends from a drain and is electrically connected to the pixel electrode. The overcoat layer is disposed between the pixel electrode and the capacitor electrode. The first common electrode overlaps the capacitor electrode, and is located between the overcoat layer and the capacitor electrode.