Abstract: Disclosed in the present application a method for electing a master node in a cluster.

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.

Abstract: This invention discloses a display panel including a first substrate, light emitting elements, a touch sensing structure and a conductive layer. The light emitting elements are disposed on the first substrate. The touch sensing structure is disposed on the first substrate and on a side away from a light emitting surface of the light emitting elements. The conductive layer is disposed between the light emitting elements and the first substrate and includes contacts or at least a portion of the touch sensing structure, and the light emitting elements and the contacts are electrically connected.

Abstract: A display device including a display panel is disclosed. The display panel includes a substrate, multiple scan lines, multiple data lines, multiple pixel structures, a first gate driving circuit, and a second gate driving circuit. The pixel structures are electrically connected to the scan lines and the data lines. Multiple first output stage circuits of the first gate driving circuit disposed in a peripheral area are electrically connected to the scan lines. Multiple second output stage circuits of the second gate driving circuit disposed in the peripheral area are electrically connected to the scan lines. A channel width of a first output transistor of the first output stage circuit is greater than a channel width of a second output transistor of the second output stage circuit.

Abstract: A semiconductor device includes a substrate, a dielectric layer disposed over the substrate, and an interconnect structure extending through the dielectric layer. The dielectric layer includes a low-k dielectric material which includes silicon carbonitride having a carbon content ranging from about 30 atomic % to about 45 atomic %. The semiconductor device further includes a thermal dissipation feature extending through the dielectric layer and disposed to be spaced apart from the interconnect structure.

Abstract: An electronic device, including a first substrate, a partition wall structure, a pressurizing component, a second substrate, a shell, and multiple first conductive parts, is provided. The first substrate has a through hole, and a first surface and a second surface that are opposite to each other. The partition wall structure is disposed on the first surface and surrounds to form a first chamber. The pressurizing component is disposed on the partition wall structure and covers the first chamber. The pressurizing component includes at least a mass and a vibration membrane. The shell is disposed on the second substrate and jointly forms a second chamber with the second substrate. The first chamber is formed in the second chamber. The multiple first conductive parts are disposed between the first substrate and the second substrate. There is a gap between any two adjacent first conductive parts.

Abstract: Various implementations disclosed herein include devices, systems, and methods that generate floorplans and measurements using a three-dimensional (3D) representation of a physical environment generated based on sensor data.

Abstract: The disclosed subject matter relates generally to resistive memory devices and methods of forming the same. More particularly, the present disclosure relates to two terminal and three terminal resistive random-access (ReRAM) memory devices with a cavity arranged between electrodes.

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, removing part of the STI to form a first step on a corner of the substrate, forming a first gate oxide layer on the substrate, removing the first gate oxide layer to form a second step on the corner of the substrate, forming a second gate oxide layer on the substrate, and then forming a first gate structure on the substrate and the STI.

Abstract: A display panel including a substrate, scan lines, data lines, and pixel structures is provided. The pixel structures are electrically connected to the data lines and the scan lines. Each pixel structure includes an active device, a pixel electrode, a capacitor electrode, a common electrode, an overcoat layer, a first passivation layer and a second passivation layer. The active device is electrically connected to the pixel electrode. The capacitor electrode is electrically connected to the pixel electrode. The common electrode is located between the capacitor electrode and the pixel electrode. The common electrode, the capacitor electrode and the pixel electrode overlap with each other. The overcoat layer is disposed between the common electrode and the first passivation layer. The second passivation layer is disposed between the common electrode and the pixel electrode.

Abstract: This application discloses an information display method and apparatus, a device, a storage medium, and a program product, relating to the field of computer and Internet technologies. The method includes displaying an interface presenting a map of a geographic region; displaying at least one information label related to the geographic region in the interface, and marking a geographic location associated with the information label on the map, each information label corresponding to at least one piece of information; and displaying information corresponding to a target information label in response to an operation on the target information label.

Abstract: A patch antenna unit and an antenna array in package are provided. The patch antenna unit includes: a substrate; and two groups of stacked patches which respectively stack on the substrate, geometric axes of the two groups of stacked patches being perpendicular to each other, wherein a radiating edge of each patch in the stacked patches is shaped as a function curve, the radiating edges of the patches in different layers are shaped as integrally orthogonal function curves, and a function curve corresponding to a shape of a non-radiating edge of each patch includes a ripple function curve.

Abstract: Various implementations provide a 3D floor plan based on scanning multiple rooms. A combined, multi-room 3D floor plan may be generated from multiple 3D floor plans from distinct, non-contiguous room scans, e.g., a first scan that is distinct from a second scan. In some implementations, combining 3D floor plans utilizes a process that, during a second scan, re-localizes in the first room and then tracks the device as the device moves (e.g., as the user walks) to the second room to scan the second room. In other implementations, combining 3D floor plans is based on user input, e.g., positioning the multiple 3D floor plans relative to one another based at least in part on a user positioning graphical representations of the floor plans relative to one another on a user interface.

Abstract: Various implementations disclosed herein include devices, systems, and methods that provide a 3D room plan that combines 2D shapes representing elements of a room that are approximately planar (e.g., walls, wall openings, windows, doors, etc.) with 3D primitives representing non-planar elements (e.g., tables, chairs, appliances, etc.). A 3D room plan is a 3D representation of a room or other physical environment that generally identifies or otherwise represents 3D positions of one or more walls, floors, ceilings, other boundaries, other regions, windows, doors, openings, and 3D objects (e.g., objects having significant height, width, and depth in 3 dimensions) within the environment. For example, a 3D floor plan using 2D shapes to represent walls, windows, doors, etc. may be combined with 3D primitives such as 3D bounding boxes representing 3D objects to form a 3D room plan.

Abstract: A touch display apparatus is disclosed, which includes a touch display panel with an active area and a peripheral area. The touch display panel includes a substrate, touch electrodes, touch sensing lines, dummy touch sensing lines and transistors. The touch electrodes are disposed on the substrate and in the active area. Each touch sensing line is electrically connected to one of the touch electrodes. The touch sensing lines and the dummy touch sensing lines are in parallel with each other in the active area. The dummy touch sensing lines are electrically connected with each other. Each transistor has a first terminal, a second terminal and a control terminal. The first terminals of the transistors are electrically connected with each other, the second terminal of each transistor is electrically connected to one of the touch sensing lines, and the control terminals of the transistors are electrically connected with each other.

Abstract: A display panel includes a substrate, pixels, gate lines, a gate connecting line, a common line and a compensation electrode. The pixels are disposed on the substrate. The gate lines are disposed on the substrate and are configured to receive scan signals. The number of pixels coupled to a first gate line of the gate lines is less that the number of pixels coupled to a second gate line of the gate lines. The gate connecting line is electrically connected to the first gate line. The common line is disposed under the gate connecting line, and is configured to receive a common voltage signal. The compensation electrode is disposed over the gate connecting line, and is configured to receive the common voltage signal. The common line, the gate connecting line and the compensation electrode are overlapped.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, forming a first doped region adjacent to the STI, removing part of the STI, and then forming a first gate structure on the substrate and the STI. Preferably, the first gate structure includes a high-k dielectric layer on the substrate and a gate electrode on the high-k dielectric layer, in which the high-k dielectric layer comprises a first L-shape.

Abstract: A display panel includes a first substrate and multiple pixel structures. The pixel structure includes at least one active element, at least one pixel electrode, a first common electrode, and a second common electrode. The at least one pixel electrode includes a first sub-electrode, a second sub-electrode, and a third sub-electrode. The first sub-electrode is electrically connected to one of the at least one corresponding active element and the second sub-electrode. The third sub-electrode is electrically connected to the second sub-electrode. The first sub-electrode, the second sub-electrode, and the third sub-electrode are different layers. The first common electrode is disposed between the first sub-electrode and the first substrate, and overlaps the first sub-electrode. The second common electrode is disposed between the first sub-electrode and the third sub-electrode, and overlaps the first sub-electrode and the third sub-electrode.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.