Abstract: A guide device and an elevator system are provided by the present application. The guide device is configured to guide a compensation chain of an elevator system and includes: a fixed mechanism, which is configured to install to an elevator hoistway, for example a stationary object such as a hoistway wall, a rail or a pit ground, and provide support for the guide device; and a guide mechanism connected to the fixed mechanism; wherein in a state where the guide mechanism is subjected to an external force exceeding a preset value, the guide mechanism is capable of reciprocating in a vertical direction relative to the fixed mechanism.

Abstract: The present invention provides a display panel including a substrate, first pads, second pads, third pads, an integrated circuit chip, and a flexible printed circuit board. The substrate includes a display region and a non-display region. The first pads are disposed in the non-display region and include display signal pads used for transmitting display signals. The second pads are disposed in the non-display region, at least a portion of the second pads are disposed along a first direction, and the second pads are disposed closer to an edge of the substrate than the first pads. The third pads are disposed in the non-display region and along the first direction, and the third pads are electrically connected to the corresponding second pads. The integrated circuit chip covers and is electrically connected to the first pads and the second pads. The flexible printed circuit board is electrically connected to the third pads.

Abstract: A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).

Abstract: A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. A fluoride ion doped region is formed right below the main gate in the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).

Abstract: A touch display device is disclosed. The touch display device includes a substrate, a scan line, a data line, a scan signal line, a thin film transistor, a touch signal line and a touch electrode. The scan line, the data line, the scan signal line, the thin film transistor, the touch signal line and the touch electrode are disposed on the substrate. An extending direction of the scan line is different from an extending direction of the data line, and the scan line and the data line are electrically connected to the thin film transistor. An extending direction of the scan signal line is different from the extending direction of the scan line, and the scan signal line is electrically connected to the scan line. The touch signal line is electrically connected to the touch electrode.

Abstract: A display panel and a fabrication method thereof are provided. The display panel includes pixels, data lines and scan lines. The pixels are arranged in pixel rows and pixel columns, and each pixel has subpixels. The data lines are configured to transmit data signals to the pixels, and each data line has a non-straight and continuously curved shape or a non-straight and continuously bent shape. The scan lines are configured to sequentially transmit scan signals to the pixels. The subpixels of each pixel are coupled to different scan lines, and each data line is curved or bent with respect to a unit of one pixel. Accordingly, the display panel of the invention can avoid the problems of poor image display and vertical line (V-line) defects as well as reducing power consumption.

Abstract: A method of forming a fin forced stack inverter includes the following steps. A substrate including a first fin, a second fin and a third fin across a first active area along a first direction is provided, wherein the first fin, the second fin and the third fin are arranged side by side. A fin remove inside active process is performed to remove at least a part of the second fin in the first active area. A first gate is formed across the first fin and the third fin in the first active area along a second direction. The present invention also provides a 1-1 fin forced fin stack inverter formed by said method.

Abstract: An in-cell touch display panel includes a sensing line. A touch electrode corresponds to more than one pixel electrodes. A first insulation layer is formed on the sensing line and has a first opening to expose the sensing line. A gate of a thin film transistor (TFT) is formed on the first insulation layer. A second insulation layer is formed on a gate line and has a second opening corresponding to the first opening. A source of the TFT is formed on the second insulation layer. A third insulation layer is formed on the source and has a third opening corresponding to the second opening. The touch electrode is formed on the third insulation layer and electrically connected to the sensing line through the third opening, the second opening, and the first opening.

Abstract: A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).

Abstract: A mark pattern includes unit cells immediately adjacent to each other and arranged in a form of dot matrix to form a register mark or an identification code, wherein each unit cell has configuration identical to functional devices of pMOS and nMOS, and each unit cell includes a first active region, a second active region isolated from the first active region, and first gate structures extending along a first direction and are arranged along a second direction perpendicular to the first direction, and the first gate structures straddling the first active region and the second active region, contact structures disposed between the first gate structures on the first active region and the second active region, and via structures disposed on the contact structures and two opposite ends of the first gate structures.

Abstract: A semiconductor device may be provided, including a base layer, an insulating layer arranged over the base layer, a memory structure arranged at least partially within the insulating layer, where the memory structure may include a first electrode, a second electrode, and an intermediate element between the first electrode and the second electrode, and a resistor arranged at least partially within the insulating layer, where the resistor may be arranged in substantially a same horizontal plane with one of the first electrode and the second electrode.

Abstract: A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface.

Abstract: A memory device may be provided, including a base layer; an insulating layer arranged over the base layer, where the insulating layer may include a recess having opposing side walls; a first electrode arranged along the opposing side walls of the recess; a switching element arranged along the first electrode; a second electrode arranged along the switching element; and a capping layer arranged over the recess, where the capping layer may at least partially overlap the first electrode, the switching element and the second electrode.

Abstract: A driving method of a display panel is provided by the present invention. First, a display panel including sub-pixels, gate lines, two gate driver circuits and clock signal lines is provided. Each of the gate lines is electrically connected to a portion of the sub-pixels, and each of the gate lines is electrically connected to one of the gate driver circuits. Each of the gate driver circuits is electrically connected to a portion of the clock signal lines. Moreover, the gate driver circuits is controlled through the clock signal lines to output scan signals to the gate lines in a plurality of frames. Furthermore, make the gate driver circuits have a first scan order in a first frame, and make the gate driver circuits have a second scan order in a second frame, and the first scan order is different from the second scan order.

Abstract: A semiconductor device may be provided, including a base layer, an insulating layer arranged over the base layer, a memory structure arranged at least partially within the insulating layer, where the memory structure may include a first electrode, a second electrode, and an intermediate element between the first electrode and the second electrode, and a resistor arranged at least partially within the insulating layer, where the resistor may be arranged in substantially a same horizontal plane with one of the first electrode and the second electrode.

Abstract: A memory device may be provided, including a base layer; an insulating layer arranged over the base layer, where the insulating layer may include a recess having opposing side walls; a first electrode arranged along the opposing side walls of the recess; a switching element arranged along the first electrode; a second electrode arranged along the switching element; and a capping layer arranged over the recess, where the capping layer may at least partially overlap the first electrode, the switching element and the second electrode.

Abstract: A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface.

Abstract: A patch antenna unit and an Antenna in Package (AIP) structure are provided. The patch antenna unit includes: a base substrate; multiple layers of patches stacked on the base substrate, wherein an isolation layer is disposed between adjacent layers of the patches, and configured to generate a radio frequency electromagnetic field, wherein an edge shape of at least one layer in the multiple layers of patches is a continuous and smooth function curve shape, and edge shapes of all sides of a same layer in the multiple layers of patches are a same function curve shape. Impedance bandwidth may be increased while symmetry of the antenna structure is maintained, and requirements of a substrate process are met, thereby increasing operation bandwidth of the AiP structure.

Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including an opening in a dielectric structure, the opening having a sidewall, a first electrode on the sidewall of the opening, a spacer layer on the first electrode, a resistive layer on the first electrode and upon an upper surface of the spacer layer, and a second electrode on the resistive layer.

Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices incorporating reference cells for achieving high sensing yield. The present disclosure provides a memory device including a main cell structure including a switching element arranged between a pair of conductors, and a reference cell structure electrically coupled to the main cell structure. The reference cell structure includes a switching element arranged between a pair of conductors, in which the switching element of the reference cell structure has a dimension that is different from a dimension of the switching element of the main cell structure.