Abstract: Various implementations disclosed herein include devices, systems, and methods that generate floorplans and measurements using a three-dimensional (3D) representation of a physical environment generated based on sensor data.

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle, a top view of the first metal interconnection includes a flat oval overlapping the circle, and the MTJ includes a bottom electrode, a fixed layer, a free layer, a capping layer, and a top electrode.

Abstract: A semiconductor device includes: a substrate having a magnetic tunneling junction (MTJ) region and a logic region; a magnetic tunneling junction (MTJ) on the MTJ region, wherein a top view of the MTJ comprises a circle; and a first metal interconnection on the MTJ. Preferably, a top view of the first metal interconnection comprises a flat oval overlapping the circle.

Abstract: A dynamic baseline position domain monitoring system based on satellite navigation and inertial navigation is used to perform a method, including: a) determining a coordinate system and a transformation matrix; b) calculating a theoretical coordinate value of an antenna baseline vector in a earth-centered earth-fixed coordinate system during the movement of a base station carrier; c) determining the number of antenna baseline vectors to be monitored; d) solving the measurement values of the antenna baseline vectors; e) calculating the position domain error of an antenna baseline vector change rate in three directions of x, y and z at epoch k, and normalizing the position domain errors to obtain a normalized value of the position domain errors; f) obtaining the a cumulative sum; g) comparing the cumulative sum with an error monitoring threshold value, and issuing an integrity risk alarm.

Abstract: An in-cell touch display panel includes a sensing line. A touch electrode corresponds to more than one pixel electrodes. A first insulation layer is formed on the sensing line and has a first opening to expose the sensing line. A gate of a thin film transistor (TFT) is formed on the first insulation layer. A second insulation layer is formed on a gate line and has a second opening corresponding to the first opening. A source of the TFT is formed on the second insulation layer. A third insulation layer is formed on the source and has a third opening corresponding to the second opening. The touch electrode is formed on the third insulation layer and electrically connected to the sensing line through the third opening, the second opening, and the first opening.

Abstract: A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface.

Abstract: A guide device and an elevator system are provided by the present application. The guide device is configured to guide a compensation chain of an elevator system and includes: a fixed mechanism, which is configured to install to an elevator hoistway, for example a stationary object such as a hoistway wall, a rail or a pit ground, and provide support for the guide device; and a guide mechanism connected to the fixed mechanism; wherein in a state where the guide mechanism is subjected to an external force exceeding a preset value, the guide mechanism is capable of reciprocating in a vertical direction relative to the fixed mechanism.

Abstract: Beam detection method and device, beam adjusting method and device, antenna module selection method and device, and computer readable storage media are provided. The antenna module selection method is applied in a terminal device including first and second AiPs, and the method includes: the ULA array in the first AiP detecting signals emitted by the UPA array in the first AiP, and comparing detected characteristic parameter values of the signals emitted by the UPA array in the first AiP withe a first preset group of characteristics parameter values, the ULA array in the second AiP detecting signals emitted by the UPA array in the second AiP, and comparing detected characteristic parameter values of the signals emitted by the UPA array in the second AiP with a second preset group of characteristic parameter values: determining to use the first or second AiP for signal transmission and reception based on the comparison.

Abstract: An antenna unit, an antenna system and an electronic device are provided. The antenna unit includes: a helical antenna with a three-dimensional structure, wherein the helical antenna is disposed on an edge region of a carrier board, and includes at least one turn of helical coil, wherein each of the at least one turn of helical coil includes multiple helical segments that are not in a same plane, and the multiple helical segments are respectively disposed in multiple layers of the carrier board. The antenna system includes a carrier board, a first antenna array and a second antenna array, wherein the first antenna array is disposed in a middle region of the carrier board and includes multiple patch units, the second antenna array includes at least one above antenna unit, and the helical antenna of the antenna unit is disposed at the edge region of the carrier board.

Abstract: A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).

Abstract: The present invention provides a display panel including a substrate, first pads, second pads, third pads, an integrated circuit chip, and a flexible printed circuit board. The substrate includes a display region and a non-display region. The first pads are disposed in the non-display region and include display signal pads used for transmitting display signals. The second pads are disposed in the non-display region, at least a portion of the second pads are disposed along a first direction, and the second pads are disposed closer to an edge of the substrate than the first pads. The third pads are disposed in the non-display region and along the first direction, and the third pads are electrically connected to the corresponding second pads. The integrated circuit chip covers and is electrically connected to the first pads and the second pads. The flexible printed circuit board is electrically connected to the third pads.

Abstract: A mark pattern includes unit cells immediately adjacent to each other and arranged in a form of dot matrix to form a register mark or an identification code, wherein each unit cell has configuration identical to functional devices of pMOS and nMOS, and each unit cell includes a first active region, a second active region isolated from the first active region, and first gate structures extending along a first direction and are arranged along a second direction perpendicular to the first direction, and the first gate structures straddling the first active region and the second active region, contact structures disposed between the first gate structures on the first active region and the second active region, and via structures disposed on the contact structures and two opposite ends of the first gate structures.

Abstract: A semiconductor device includes: a substrate having a magnetic tunneling junction (MTJ) region and a logic region; a magnetic tunneling junction (MTJ) on the MTJ region, wherein a top view of the MTJ comprises a circle; and a first metal interconnection on the MTJ. Preferably, a top view of the first metal interconnection comprises a flat oval overlapping the circle.

Abstract: The application relates to a method and system for tracking a target object in a video. The method includes: extracting, from the video, a 3-dimension (3D) feature block containing the target object; decomposing the extracted 3D feature block into a 2-dimension (2D) spatial feature map containing spatial information of the target object and a 2D spatial-temporal feature map containing spatial-temporal information of the target object; estimating, in the 2D spatial feature map, a location of the target object; determining, in the 2D spatial-temporal feature map, a speed and an acceleration of the target object; calibrating the estimated location of the target object according to the determined speed and acceleration; and tracking the target object in the video according to the calibrated location.

Abstract: A touch display device including a display region and a peripheral region comprises a substrate, a plurality of scan lines and a plurality of data lines disposed on the substrate, a plurality of thin film transistors disposed on the substrate, a plurality of pixel electrodes disposed on the substrate and in the display region, and a plurality of touch electrodes and a plurality of touch signal lines disposed on the substrate. In the display region, three data lines of the plurality of data lines are located between two touch signal lines of the plurality of touch signal lines, and in the peripheral region, one of the two touch signal lines is at least partially overlapped with one of the three data lines, and two other data lines of the three data lines are at least partially overlapped with each other.

Abstract: A semiconductor device includes a substrate including a plurality of chip areas and a scribe line defined thereon, and a mark pattern disposed in the scribe line. The mark pattern includes a plurality of unit cells immediately adjacent to each other, and each unit cell includes a first active region, a second active region isolated from the first active region, a plurality of first gate structures extending along a first direction and arranged along a second direction perpendicular to the first direction, and a plurality of first conductive structures. The first gate structures straddle the first active region and the second active region. The first conductive structures are disposed on the first active region, the second active region, and two opposite sides of the first gate structures.

Abstract: A touch display device includes thin film transistors, a first insulating layer, a first transparent conductive layer, a second insulating layer, contact holes, a second transparent conductive layer, and touch signal lines. The first transparent conductive layer includes pixel electrodes, and each pixel electrode is electrically connected to a drain of one of the thin film transistors. The contact holes penetrate the first insulating layer and the second insulating layer. Each contact hole exposes a portion of the pixel electrode and a portion of the drain. The second transparent conductive layer includes touch electrodes and connecting electrodes. Each connecting electrode extends into one of the contact holes, and is in contact with the portion of the pixel electrode and the portion of the drain. Each touch signal line is electrically to a corresponding touch electrode.

Abstract: A magnetic random access memory (MRAM) includes device strings coupled in parallel, each comprising magnetic tunnel junctions (MTJs) coupled in serial, wherein a quantity of the MTJs of each of the device strings is equal to a quantity of the device strings, and an equivalent resistance (Req) of the MTJs is equal to an average of the sum of a high resistance of one of the MTJs and a low resistance of another MTJ.

Abstract: A semiconductor device includes: a dummy gate on a substrate; a first control gate on one side of the dummy gate and a second control gate on another side of the dummy gate; a well in the substrate, wherein the well comprises a first conductive type; a first source/drain region between the dummy gate and the first control gate, wherein the first source/drain region comprises a second conductive type; a second source/drain region between the dummy gate and the second control gate, wherein the second source/drain region comprises the second conductive type; and a doped region directly under the dummy gate, wherein the doped region comprises the first conductive type.

Abstract: A semiconductor device includes: a dummy gate on a substrate; a first control gate on one side of the dummy gate and a second control gate on another side of the dummy gate; a well in the substrate, wherein the well comprises a first conductive type; a first source/drain region between the dummy gate and the first control gate, wherein the first source/drain region comprises a second conductive type; a second source/drain region between the dummy gate and the second control gate, wherein the second source/drain region comprises the second conductive type; and a doped region directly under the dummy gate, wherein the doped region comprises the first conductive type.