Patents by Inventor Kai-Lin Lee
Kai-Lin Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200295176Abstract: A semiconductor structure includes at least one stacked fin structure, a gate and a source/drain. At least one stacked fin structure is located on a substrate, wherein the stacked fin structure includes a first fin layer and a second fin layer, and a fin dielectric layer is sandwiched by the first fin layer and the second fin layer. The gate is disposed over the stacked fin structure. The source/drain is disposed directly on the substrate and directly on sidewalls of the whole stacked fin structure. The present invention provides a semiconductor process formed said semiconductor structure.Type: ApplicationFiled: March 22, 2019Publication date: September 17, 2020Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
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Patent number: 10756209Abstract: A semiconductor device including a substrate having a fin structure surrounded by a trench isolation region; a trench disposed in the fin structure; an interlayer dielectric layer disposed on the substrate; a working gate striding over the fin structure and on the first side of the trench; a dummy gate striding over the fin structure and on the second side of the trench; a doped source region in the fin structure; and a doped drain region in the fin structure. The dummy gate is disposed between the trench and the doped drain region. The fin structure extends along a first direction and the dummy gate extends along a second direction. The first direction is not parallel with the second direction.Type: GrantFiled: March 8, 2020Date of Patent: August 25, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
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Publication number: 20200220011Abstract: A semiconductor device including a substrate having a fin structure surrounded by a trench isolation region; a trench disposed in the fin structure; an interlayer dielectric layer disposed on the substrate; a working gate striding over the fin structure and on the first side of the trench; a dummy gate striding over the fin structure and on the second side of the trench; a doped source region in the fin structure; and a doped drain region in the fin structure. The dummy gate is disposed between the trench and the doped drain region. The fin structure extends along a first direction and the dummy gate extends along a second direction. The first direction is not parallel with the second direction.Type: ApplicationFiled: March 8, 2020Publication date: July 9, 2020Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
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Publication number: 20200135582Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a first gate structure and a second gate structure on the first fin-shaped structure; using a patterned mask to remove the first gate structure and part of the first fin-shaped structure to form a first trench; and forming a first dielectric layer in the first trench to form a first single diffusion break (SDB) structure and around the second gate structure.Type: ApplicationFiled: December 23, 2019Publication date: April 30, 2020Inventors: Zhi-Cheng Lee, Kai-Lin Lee, Wei-Jen Chen
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Patent number: 10629734Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.Type: GrantFiled: January 18, 2019Date of Patent: April 21, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
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Patent number: 10629728Abstract: A semiconductor device including a substrate having a fin structure surrounded by a trench isolation region; a trench disposed in the fin structure; a silicon nitride trench-fill layer disposed in the trench; an interlayer dielectric layer disposed on the silicon nitride trench-fill layer; a working gate striding over the fin structure, on the first side of the trench; a dummy gate striding over the fin structure, on the second side of the trench; a doped source region in the fin structure; and a doped drain region in the fin structure. The dummy gate is disposed between the trench and the doped drain region.Type: GrantFiled: January 20, 2019Date of Patent: April 21, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
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Patent number: 10566244Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a first gate structure and a second gate structure on the first fin-shaped structure; using a patterned mask to remove the first gate structure and part of the first fin-shaped structure to form a first trench; and forming a first dielectric layer in the first trench to form a first single diffusion break (SDB) structure and around the second gate structure.Type: GrantFiled: August 1, 2018Date of Patent: February 18, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Kai-Lin Lee, Wei-Jen Chen
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Publication number: 20200006153Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a first gate structure and a second gate structure on the first fin-shaped structure; using a patterned mask to remove the first gate structure and part of the first fin-shaped structure to form a first trench; and forming a first dielectric layer in the first trench to form a first single diffusion break (SDB) structure and around the second gate structure.Type: ApplicationFiled: August 1, 2018Publication date: January 2, 2020Inventors: Zhi-Cheng Lee, Kai-Lin Lee, Wei-Jen Chen
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Publication number: 20190172949Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.Type: ApplicationFiled: January 18, 2019Publication date: June 6, 2019Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
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Patent number: 10229995Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.Type: GrantFiled: August 4, 2017Date of Patent: March 12, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
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Publication number: 20190027602Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.Type: ApplicationFiled: August 4, 2017Publication date: January 24, 2019Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
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Publication number: 20180358453Abstract: The present invention provides a method of making a tunneling effect transistor (TFET), the method includes: a substrate is provided, having a fin structure disposed thereon, the fin structure includes a first conductive type, a dielectric layer is then formed on the substrate and on the fin structure, a gate trench is formed in the dielectric layer, and a first work function metal layer is formed in the gate trench, the first work function metal layer defines at least a left portion, a right portion and a central portion, an etching process is performed to remove the central portion of the first work function metal layer, and to form a recess between the left portion and the right portion of the first work function metal layer, afterwards, a second work function metal layer is formed and filled in the recess.Type: ApplicationFiled: July 6, 2017Publication date: December 13, 2018Inventors: Hung-Wen Huang, Kai-Lin Lee, Ren-Yu He, Chi-Hsiao Chen, Ting-Hsuan Kang, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
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Patent number: 10103265Abstract: A CMOS device is disclosed, including a plurality of active regions having a length along a first direction, wherein the active regions are arranged end-to-end along the first direction and are separated by an isolation structure. A recessed region is formed in the isolation structure between the adjacent terminals of the each pair of neighboring active regions and is completely filled by an interlayer dielectric layer, wherein the interlayer dielectric layer comprises a stress.Type: GrantFiled: September 6, 2017Date of Patent: October 16, 2018Assignee: UNITED MICROELETRONICS CORP.Inventors: Zhi-Cheng Lee, Kai-Lin Lee, Yi-Che Yen
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Patent number: 10014406Abstract: A semiconductor device and a forming method thereof, the semiconductor device includes a first and a second wells, a source region, a drain region, two gate structures and at least one doping region. The first well with a first conductive type is disposed in a substrate, and the source region is disposed in the first well. The second well with a second conductive type is disposed adjacent to the first well in a substrate, and the drain region is disposed in the second well. Two gate structures are disposed on the substrate between the source region and the drain region. At least one doping region with the first conductive type is disposed in the second well between the two gate structures.Type: GrantFiled: August 16, 2016Date of Patent: July 3, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Yu-Hao Huang, Kai-Lin Lee
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Publication number: 20180166574Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first epitaxial layer adjacent to two sides of the gate structure; forming a patterned mask on the epitaxial layer; and using the patterned mask to remove part of the first epitaxial layer for forming a second epitaxial layer.Type: ApplicationFiled: December 8, 2016Publication date: June 14, 2018Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Chih-Chun Hu
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Publication number: 20180012992Abstract: A semiconductor device and a forming method thereof, the semiconductor device includes a first and a second wells, a source region, a drain region, two gate structures and at least one doping region. The first well with a first conductive type is disposed in a substrate, and the source region is disposed in the first well. The second well with a second conductive type is disposed adjacent to the first well in a substrate, and the drain region is disposed in the second well. Two gate structures are disposed on the substrate between the source region and the drain region. At least one doping region with the first conductive type is disposed in the second well between the two gate structures.Type: ApplicationFiled: August 16, 2016Publication date: January 11, 2018Inventors: Zhi-Cheng Lee, Yu-Hao Huang, Kai-Lin Lee
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Patent number: 9640661Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a fin-shaped structure is formed on the substrate. Next, a gate structure is formed on the fin-shaped structure, and an epitaxial layer is formed adjacent to the gate structure. Preferably, the epitaxial layer includes a V-shaped profile viewing from the top. According to the preferred embodiment of the present invention, the V-shaped profile of the epitaxial layer allows more stress to be applied to the region having concentrated currents or edges of the fin-shaped structures during an on-state, and at the same time prevent exerting too much stress to the region having high currents or central region of the fin-shaped structure during an off-state.Type: GrantFiled: May 3, 2016Date of Patent: May 2, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Yu-Hao Huang
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Patent number: 9450094Abstract: A semiconductor process includes the following steps. A fin on a substrate is provided. Spacers are formed only on sidewalls of the fin, where a top surface of the fin is higher than or equal to top surfaces of the spacers. An epitaxial structure is formed on the fin. The present invention also provides a fin-shaped field effect transistor including a fin, spacers and an epitaxial structure. The fin is located on a substrate. The spacers are disposed only on sidewalls of the fin, where a top surface of the fin is higher than or equal to top surfaces of the spacers. The epitaxial structure is disposed on the fin.Type: GrantFiled: September 8, 2015Date of Patent: September 20, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Chieh Yeh, Kai-Lin Lee