Patents by Inventor Kai Yang

Kai Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250258271
    Abstract: A radar system and control method thereof is disclosed. The radar system comprises a plurality of radar units, each comprising: one or more radio frequency (RF) channels configured to receive a reflected signal and then generate an analog input signal according to the reflected signal; and a processing module connected with all the RF channels and configured to sample the analog input signal to obtain a digital signal and perform the first digital signal processing on the digital signal to obtain intermediate data, wherein when the plurality of radar units work jointly, a designated radar unit performs the second digital signal processing on the plurality of intermediate data provided by the plurality of radar units, thereby obtaining result data of the radar system.
    Type: Application
    Filed: April 3, 2025
    Publication date: August 14, 2025
    Inventors: Yi Chen, Yan Zhu, Jiashu Chen, Leilei Huang, Wenting Zhou, Zhonglei Hao, Kai Yang, Pengfei Jiang, Zhengdong Liu
  • Patent number: 12382988
    Abstract: A cigar cutter with a positioning mechanism keeping it in an open or closed state includes a rotatable ring, an elastic element, an arresting block and a guide track. Pressing the cigar cutter's cutting blade unit(s) drives the rotatable ring to rotate to compress the elastic element, and the arresting block touches an abutting block and a shoulder in the guide track and is engaged to one end of the guide track, so the cigar cutter is in the closed state. Pressing the cutting blade unit(s) again drives the rotatable ring to rotate to compress the elastic element, the arresting block again touches the abutting block and shoulder and is out of the engaged state, and the elastic element drives the rotatable ring to rotate reversely, which moves the arresting block to the other end of the guide track and allows the cigar cutter to enter the open state.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: August 12, 2025
    Inventor: Chun-Kai Yang
  • Patent number: 12389646
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes nanostructures spaced apart from each other in a first direction and a gate structure formed over and around the nanostructures. The semiconductor structure further includes a gate spacer covering a sidewall of the gate structure and a source/drain structure attached to the nanostructures in a second direction. The semiconductor structure further includes a contact spaced apart from the gate structure by the gate spacer in the second direction and a first conductive structure landing over the gate structure. The semiconductor structure further includes a second conductive structure formed over the gate spacer. In addition, a portion of the second conductive structure is sandwiched between the first conductive structure and the contact.
    Type: Grant
    Filed: March 14, 2024
    Date of Patent: August 12, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jia-Heng Wang, Pang-Chi Wu, Chao-Hsun Wang, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20250253757
    Abstract: A multi-phase power converter converts an input voltage into an output voltage to supply power to a load, and the multi-phase power includes at least two power conversion circuits, a driver circuit and a controller. The controller is configured to determine a loading condition of the multi-phase power converter according to at least one of an input current and an output current of the multi-phase power converter. When the controller determines the loading condition is not a heavy-loading condition, the controller configures the driver circuit to alternatively drive the power conversion circuits to converter the input voltage into the output voltage; the controller disables the driver circuit when the input current of the multi-phase power converter is lower than a predetermined threshold, and the controller enables the driver circuit to alternatively drive the power conversion circuits when the input current is greater than the predetermined threshold.
    Type: Application
    Filed: April 21, 2025
    Publication date: August 7, 2025
    Inventor: Shang-Kay YANG
  • Publication number: 20250254930
    Abstract: Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.
    Type: Application
    Filed: April 21, 2025
    Publication date: August 7, 2025
    Inventors: Chen-Ming Lee, Po-Yu Huang, Fu-Kai Yang, I-Wen Wu, Mei-Yun Wang
  • Patent number: 12376360
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a silicide feature disposed in the backside dielectric layer, and a source/drain feature disposed over the silicide feature and extending between the first plurality of channel members and the second plurality of channel members. The silicide feature extends through an entire depth of the backside dielectric layer.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: July 29, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hung Tsai, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20250226231
    Abstract: A method includes providing a substrate of a first conductivity type, the substrate including a first circuit region and a second circuit region; forming a first well region of a second conductivity type in the first circuit region of the substrate; forming a first doped region of the second conductivity type in the first well region; forming a diode in the second circuit region of the substrate; forming a first transistor and a second transistor over the substrate in the first circuit region and the second circuit region, respectively; forming a discharge structure over the substrate to electrically couple the first doped region to the diode; and forming a metallization layer over the discharge structure to electrically couple the first transistor to the second transistor subsequent to the forming of the diode, wherein charges accumulated in the first well region are drained to the substrate through the discharge structure.
    Type: Application
    Filed: March 27, 2025
    Publication date: July 10, 2025
    Inventors: YAO-JEN TSAI, KENG-HUI LIAO, CHIH-KAI YANG, CHIH-FU CHANG, CHIA-JEN LEU, CHIN-YUAN KO
  • Publication number: 20250226262
    Abstract: One aspect of the present disclosure pertains to a semiconductor structure. The semiconductor structure includes a first circuit area having: an active region extending lengthwise along a first direction, the active region includes a channel region between source/drain (S/D) features and a gate over the channel region, a dielectric structure over and surrounding the active region, a metal contact penetrating through a top surface of the dielectric structure to land on one of the S/D features, and a first via landing on the metal contact. The semiconductor structure includes a second circuit area having: the dielectric structure, a feedthrough via penetrating through the top surface of the dielectric structure and a bottom surface of the dielectric structure, and a second via landing on the feedthrough via. The first via and the second via have substantially coplanar bottom surfaces.
    Type: Application
    Filed: January 9, 2024
    Publication date: July 10, 2025
    Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 12354873
    Abstract: A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer. The semiconductor process system reduces a width of the photoresist structure by bombarding the photoresist structure with ions in multiple distinct ion bombardment steps having different characteristics.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: July 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Kai Yang, Yu-Tien Shen, Hsiang-Ming Chang, Chun-Yen Chang, Ya-Hui Chang, Wei-Ting Chien, Chia-Cheng Chen, Liang-Yin Chen
  • Patent number: 12347681
    Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: July 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng Chen, Chun-Hung Wu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Chun-Yen Chang, Chih-Kai Yang, Yu-Tien Shen, Ya Hui Chang
  • Publication number: 20250206271
    Abstract: An all-terrain vehicle may include a frame and a plurality of ground-engaging members supporting the frame. The all-terrain vehicle may further include a powertrain assembly supported by the frame and shiftable transmission supported by the frame and operably coupled to the powertrain assembly. The all-terrain vehicle may also include a display, a back-up camera, and a controller supported by the frame. The controller may be configured to receive a signal from the shiftable transmission corresponding to the shiftable transmission being in a gear of the plurality of gears other than a reverse gear. Further, the controller may be configured to determine the all-terrain vehicle is moving backwards and send an activation signal to the back-up camera to display images of the back-up camera on the display.
    Type: Application
    Filed: February 21, 2025
    Publication date: June 26, 2025
    Inventors: Aidan Shaughnessy, Kai Yang, Joseph P. Nuxoll, Jonathon P. Graus, Lester Lee, Jacob H. Larson
  • Patent number: 12337876
    Abstract: A collision detection method, an electronic device, and a storage medium are provided, which relate to a field of artificial intelligence technology, and in particular to fields of intelligent transportation and autonomous driving technologies. The method includes: determining a predicted travel range of a target object based on a planned travel trajectory of the target object and a historical travel trajectory of the target object; determining, in response to a target obstacle being detected, a predicted travel range of the target obstacle based on a current travel state of the target obstacle; and determining whether the target object has a risk of colliding with the target obstacle, based on the predicted travel range of the target object and the predicted travel range of the target obstacle.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: June 24, 2025
    Assignee: Beijing Baidu Netcom Science Technology Co., Ltd.
    Inventors: Lei Zhang, Kai Yang, Qijuan Yin, Wuzhao Zhang, Xiaoyan Wang
  • Patent number: 12340286
    Abstract: A model management system adaptively refines a training dataset for more effective visual inspection. The system trains a machine learning model using the initial training dataset and sends the trained model to a client for deployment. The deployment process generates outputs that are sent back to the system. The system determines that performance of predictions for noisy data points are inadequate and determines a cause of failure based on a mapping of the noisy data point to a distribution generated for the training dataset across multiple dimensions. The system determines a cause of failure based on an attribute of the noisy datapoint that deviates from the distribution of the training dataset and performs refinement towards the training dataset based on the identified cause of failure. The system retrains the machine learning model with the refined training dataset and sends the retrained machine learning model back to the client for re-deployment.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: June 24, 2025
    Assignee: LandingAI Inc.
    Inventors: Daniel Bibireata, Andrew Yan-Tak Ng, Pingyang He, Zeqi Qiu, Camilo Iral, Mingrui Zhang, Aldrin Leal, Junjie Guan, Ramesh Sampath, Dillon Laird, Yu Qing Zhou, Juan Camilo Fernancez, Camilo Zapata, Sebastian Rodriguez, Cristobal Silva, Sanjay Bodhu, Mark William Sabini, Leela Seshu Reddy Cheedepudi, Kai Yang, Yan Liu, Whit Blodgett, Ankur Rawat, Francisco Matias Cuenca-Acuna, Quinn Killough
  • Publication number: 20250196812
    Abstract: A windshield wiper assembly structure includes a wiper holder, a wiper blade, elastic sheets, and clamping seats. The wiper holder includes two outer buckling brackets. Each outer buckling bracket includes a through groove and an opening. The wiper blade includes a penetrating portion and a scraping portion. The penetrating portion is inserted in the through grooves. The penetrating portion includes a central column and a first slot. The elastic sheets are respectively inserted to first slots. Each elastic sheet is attached to the central column and abuts against the outer buckling brackets. The clamping seats are fixed on ends of the wiper blade. Each clamping seat includes a pair of clipping plates and clamped by the outer buckling brackets. Each clipping plate includes a protruding thorn and inserted to the first slot to abut against the elastic sheets. The protruding thorn passes through the central column.
    Type: Application
    Filed: March 4, 2025
    Publication date: June 19, 2025
    Inventors: Che-Wei CHANG, Cheng-Kai YANG, Chuan-Chih CHANG
  • Patent number: 12334388
    Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece including a semiconductor fin protruding from a substrate, a first placeholder gate and a second placeholder gate over channel regions of the semiconductor fin, and a source/drain feature disposed between the channel regions. The method also includes removing a portion of the first placeholder gate and a portion of the substrate directly disposed thereunder to form an isolation trench, forming a dielectric feature in the isolation trench, replacing the second placeholder gate with a metal gate stack, selectively recessing the dielectric feature, forming a first capping layer over the metal gate stack and a second capping layer over the recessed dielectric feature, and forming a source/drain contact over and electrically coupled to the source/drain feature.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: June 17, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: I-Wen Wu, Po-Yu Huang, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 12333792
    Abstract: A model management system performs error analysis on results predicted by a machine learning model. The model management system identifies an incorrectly classified image outputted from a machine learning model and identifies using the Neural Template Matching (NTM) algorithm, an additional image correlated to the selected image. The system outputs correlated images based on a given image and a selection by a user through a user interface of a region of interest (ROI) of the given image. The region is defined by a bounding polygon input and the correlated images include features correlated to the features within the ROI. The system prompts a task associated with the additional image. The system receives a response that includes an indication that the additional image is incorrectly labeled and including a replacement label and instruct that the machine learning model be retrained using an updated training dataset that includes the replacement label.
    Type: Grant
    Filed: October 21, 2022
    Date of Patent: June 17, 2025
    Assignee: LandingAI Inc.
    Inventors: Mark William Sabini, Kai Yang, Andrew Yan-Tak Ng, Daniel Bibireata, Dillon Laird, Whitney Blodgett, Yan Liu, Yazhou Cao, Yuxiang Zhang, Gregory Diamos, YuQing Zhou, Sanjay Boddhu, Quinn Killough, Shankaranand Jagadeesan, Camilo Zapata, Sebastian Rodriguez
  • Publication number: 20250185330
    Abstract: A semiconductor structure and a method of forming the same are provided. An exemplary method of forming the semiconductor structure includes forming a semiconductor sacrificial plug in a substrate, forming a transistor over the substrate and on the semiconductor sacrificial plug, performing a pre-amorphous implantation (PAI) process from a back side of the substrate to amorphize at least a portion of the substrate, replacing the substrate with a dielectric layer, and replacing the semiconductor sacrificial plug with a backside contact. The semiconductor sacrificial plug and the substrate have different compositions. The transistor includes a source region and a drain region, a channel region disposed between the source region and the drain region, and a gate structure disposed over the channel region.
    Type: Application
    Filed: February 10, 2025
    Publication date: June 5, 2025
    Inventors: Po-Yu Huang, Chen-Ming Lee, Fu-Kai Yang, I-Wen Wu, Mei-Yun Wang
  • Patent number: 12324202
    Abstract: A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a gate structure formed over and around the nanostructures. The structure also includes a spacer layer formed over a sidewall of the gate structure over the nanostructures. The structure also includes a source/drain epitaxial structure formed adjacent to the spacer layer. The structure also includes a contact structure formed over the source/drain epitaxial structure with an air spacer formed between the spacer layer and the contact structure.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: June 3, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Hsuan Lee, Shih-Che Lin, Po-Yu Huang, Shih-Chieh Wu, I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: D1078833
    Type: Grant
    Filed: July 4, 2024
    Date of Patent: June 10, 2025
    Inventors: Kai Yang, Jun Wang, Yan Ke
  • Patent number: D1086227
    Type: Grant
    Filed: May 17, 2024
    Date of Patent: July 29, 2025
    Inventors: Jianbo Tian, Hongwei Zhu, Kai Yang