Patents by Inventor Kai Yang

Kai Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Epitaxial source/drain structure and method
    Patent number: 11784222
    Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chun-An Lin, Wei-Yuan Lu, Guan-Ren Wang, Peng Wang
  • SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME
    Publication number: 20230317805
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a gate electrode layer disposed over a substrate, a source/drain epitaxial feature disposed over the substrate, a first hard mask layer disposed over the gate electrode layer, and a contact etch stop layer (CESL) disposed over the source/drain epitaxial feature. The structure further includes a first interlayer dielectric (ILD) layer disposed on the CESL and a first treated portion of a second hard mask layer disposed on the CESL and the first ILD layer. A top surface of the first hard mask layer and a top surface of the first treated portion of the second mask layer are substantially coplanar. The structure further includes an etch stop layer disposed on the first hard mask layer and the first treated portion of the second mask layer.
    Type: Application
    Filed: March 21, 2022
    Publication date: October 5, 2023
    Inventors: Shih-Che LIN, Tzu-Yang HO, Chen-Ming LEE, Fu-Kai YANG, Mei-Yun WANG
  • Method of forming a semiconductor device
    Patent number: 11776810
    Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Cheng Chen, Chun-Hung Wu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Chun-Yen Chang, Chih-Kai Yang, Yu-Tien Shen, Ya Hui Chang
  • Fin field effect transistor (FinFET) device structure and method for forming the same
    Patent number: 11777004
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a first inter-layer dielectric (ILD) layer formed over the fin structure. The FinFET device structure includes a gate structure formed in the first ILD layer, and a first S/D contact structure formed in the first ILD layer and adjacent to the gate structure. The FinFET device structure also includes a first air gap formed on a sidewall of the first S/D contact structure, and the first air gap is in direct contact with the first ILD layer.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: October 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Hsuan Lee, I-Wen Wu, Chen-Ming Lee, Jian-Hao Chen, Fu-Kai Yang, Feng-Cheng Yang, Mei-Yun Wang, Yen-Ming Chen
  • Sealed type windshield wiper structure
    Patent number: 11766996
    Abstract: This disclosure provides a sealed type windshield wiper structure (1). The carrying seat (20) is combined on the hooking seat (10). The carrying seat (20) includes a carrying board (21) and a carrying frame (22). The carrying board (21) includes a through slot (210), and the carrying frame (22) includes an accommodating slot (220). The elastic piece (30) is inserted in the through slot (210). The waterproof cover (40) includes a shell (41), an inner space (32) and an outer space (43) The carrying seat (20) is inserted in the inner space (42). The rubber wiper (50) includes a piercing strip (51) and a scraping strip (52). The piercing strip (51) is inserted in the outer space (43), and the scraping strip (52) is exposed from the waterproof cover (40) to configure the sealed type windshield wiper structure (1).
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: September 26, 2023
    Assignee: DANYANG UPC AUTO PARTS CO., LTD.
    Inventors: Che-Wei Chang, Cheng-Kai Yang, Chuan-Chih Chang
  • Assembling structure of wiper accessory seat
    Patent number: 11760311
    Abstract: An assembling structure of wiper accessory seat includes an accessory seat and metal elastic sheets. The bottom portion of the accessory seat is formed with a recess, first fixing portions and second fixing portions. The first fixing portions and the second fixing portions are symmetrically disposed on two opposite sides of the recess and arranged spacedly in an upper-bottom manner. The metal elastic sheets are disposed with third fixing portions, separately inserted between the first fixing portions and the second fixing portions, and connected to the bottom portion of the accessory seat by the third fixing portions being positioned on the first fixing portions and the second fixing portions being positioned on the metal elastic sheets so as to simplify the assembling structure.
    Type: Grant
    Filed: November 15, 2022
    Date of Patent: September 19, 2023
    Assignee: DANYANG UPC AUTO PARTS CO., LTD.
    Inventors: Che-Wei Chang, Cheng-Kai Yang, Chuan-Chih Chang
  • ASSEMBLING STRUCTURE OF WIPER ACCESSORY SEAT
    Publication number: 20230286468
    Abstract: An assembling structure of wiper accessory seat includes an accessory seat and metal elastic sheets. The bottom portion of the accessory seat is formed with a recess, first fixing portions and second fixing portions. The first fixing portions and the second fixing portions are symmetrically disposed on two opposite sides of the recess and arranged spacedly in an upper-bottom manner. The metal elastic sheets are disposed with third fixing portions, separately inserted between the first fixing portions and the second fixing portions, and connected to the bottom portion of the accessory seat by the third fixing portions being positioned on the first fixing portions and the second fixing portions being positioned on the metal elastic sheets so as to simplify the assembling structure.
    Type: Application
    Filed: November 15, 2022
    Publication date: September 14, 2023
    Inventors: Che-Wei CHANG, Cheng-Kai YANG, Chuan-Chih CHANG
  • Parasitic capacitance reduction
    Patent number: 11757022
    Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottom surface of the gate structure is closer to the substrate than a bottom surface of the source/drain contact.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Heng Wang, Chun-Han Chen, I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Fin field effect transistor (FinFET) device structure with deep contact structure
    Patent number: 11742400
    Abstract: A FinFET device structure and method for forming the same is provided. The FinFET device structure includes an isolation structure formed over a substrate, and a gate structure formed over the isolation structure. The FinFET device structure includes a first dielectric layer formed over the isolation structure and adjacent to the gate structure and a source/drain (S/D) contact structure formed in the first dielectric layer. The FinFET device structure also includes a deep contact structure formed through the first dielectric layer and adjacent to the S/D contact structure. The deep contact structure is through the isolation structure, and a bottom surface of the S/D contact structure is higher than a bottom surface of the deep contact structure.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting Fang, Da-Wen Lin, Fu-Kai Yang, Chen-Ming Lee, Mei-Yun Wang
  • SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20230268411
    Abstract: A semiconductor structure includes a substrate, nanostructures over the substrate, and a gate structure wrapping around the nanostructures. The gate structure includes a gate dielectric layer and a gate electrode wrapping around the gate dielectric layer. The semiconductor structure further includes a source/drain feature in contact with the nanostructures, a contact etch stop layer over the source/drain feature, and a seal layer over the air spacer and the gate structure, and on a sidewall of the contact etch stop layer. The contact etch stop layer is separated from the gate structure by an air spacer.
    Type: Application
    Filed: February 23, 2022
    Publication date: August 24, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Hsuan LEE, Shih-Che LIN, Po-Yu HUANG, Shih-Chieh WU, I-Wen WU, Chen-Ming LEE, Fu-Kai YANG, Mei-Yun WANG
  • Heat dissipation apparatus, remote radio unit, baseband processing unit and base station
    Patent number: 11737241
    Abstract: A heat dissipation apparatus, a remote radio unit, a baseband processing unit and a base station are disclosed. According to an embodiment, the heat dissipation apparatus comprises a base and a plurality of first heat sink fins arranged in parallel on the base. On a top of each first heat sink fin of the plurality of first heat sink fins, a first heat dissipation component and a second heat dissipation component are sequentially arranged along the parallel direction of the plurality of first heat sink fins. The first heat dissipation component comprises a bottom plate and a plurality of second heat sink fins which are arranged at intervals along the parallel direction on a top face of the bottom plate. Each second heat sink fin has a shape of a comb having three or more comb teeth.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: August 22, 2023
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Haigang Xiong, Kai Yang, Bo Xiao, Mengyu Huang
  • Fin field effect transistor (FinFET) device structure with protection layer and method for forming the same
    Patent number: 11735474
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The FinFET device structure includes a source/drain (S/D) structure formed over the fin structure and adjacent to the gate structure, and an S/D contact structure formed over the S/D structure and adjacent to the gate structure. The FinFET device structure also includes a protection layer formed on the S/D contact structure, and the protection layer and the S/D contact structure are made of different materials. The protection layer has a bottommost surface in direct contact with a topmost surface of the S/D contact structure.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: August 22, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Yuan Chen, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • INTERCONNECT STRUCTURES AND METHODS OF FABRICATION THEREOF
    Publication number: 20230260900
    Abstract: A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a first source/drain contact and a second source/drain contact spaced apart by a gate structure, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, a conductive feature disposed in the etch stop layer and in direct contact with the first source/drain contact and the second source/drain contact, a dielectric layer over the etch stop layer, and a contact via extending through the dielectric layer and electrically connected to the conductive feature. By providing the conductive feature, a number of metal lines in an interconnect structure of the semiconductor structure may be advantageously reduced.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 17, 2023
    Inventors: Chao-Hsun Wang, Wang-Jung Hsueh, Fu-Kai Yang, Mei-Yun Wang, Sheng-Hsiung Wang, Shih-Hsien Huang
  • CONTACT STRUCTURE WITH SILICIDE AND METHOD FOR FORMING THE SAME
    Publication number: 20230261068
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a gate electrode layer formed adjacent to the source/drain contact structure. The semiconductor device structure also includes a first spacer and a second spacer laterally and successively arranged from the sidewall of the gate electrode layer to the sidewall of the source/drain contact structure. The semiconductor device structure further includes a silicide region formed in the source/drain region. The top width of the silicide region is greater than the bottom width of the source/drain contact structure and less than the top width of the source/drain region.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 17, 2023
    Inventors: Kai-Hsuan LEE, Shih-Che LIN, Po-Yu HUANG, Shih-Chieh WU, I-Wen WU, Chen-Ming LEE, Fu-Kai YANG, Mei-Yun WANG
  • Cooling system of server
    Patent number: 11729947
    Abstract: A cooling system of server includes a tank, a case body, a multi-hole box, a first dehumidifying material, a first tube, and a second tube. The tank is configured to accommodate a dielectric fluid. The multi-hole box is disposed in the case body. The first dehumidifying material is disposed in the multi-hole box. The first tube includes a first gas-inlet/outlet end and a second gas-inlet/outlet end respectively connected to the tank and the case body. The second gas-inlet/outlet end is connected to the first dehumidifying material. The second tube includes a liquid-inlet end and a liquid-outlet end respectively connected to the case body and the tank.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: August 15, 2023
    Assignees: Inventec (Pudong) Technology Corporation, INVENTEC CORPORATION
    Inventors: Kai-Yang Tung, Hung-Ju Chen
  • Method and apparatus of determining guide path, method and apparatus of controlling driving of vehicle, and electronic device
    Patent number: 11724716
    Abstract: The present disclosure provides a method and apparatus of determining a guide path, and a method and apparatus of controlling driving of a vehicle. The method of determining the guide path may be performed by a monitoring platform and includes: displaying a map for a predetermined range of a vehicle in response to receiving a guide request transmitted by the vehicle, wherein the map includes a plurality of first track points for the vehicle; changing a position of at least one of the plurality of first track points in the map in response to a target operation on the at least one first track point, so as to obtain a plurality of second track points; determining the guide path for the vehicle according to the plurality of second track points; and transmitting path information indicative of the guide path to the vehicle.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: August 15, 2023
    Assignee: Beijing Baidu Netcom Science Technology Co., Ltd.
    Inventors: Liming Xia, Kai Yang, Jingchao Feng, Pengjie Zheng, Tianxiang Cui, Mingsong Wang, Yanting Chen, Rongjing Shang, Jiaxin Sun, Haitao Liu, Xiaochuan Du
  • Method of forming backside power rails
    Patent number: 11728394
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method of forming the semiconductor structure includes forming a fin structure extending from a front side of a substrate, recessing a source region of the fin structure to form a source opening, forming a semiconductor plug under the source opening, planarizing the substrate to expose the semiconductor plug from a back side of the substrate, performing a pre-amorphous implantation (PAI) process to amorphize the substrate, replacing the amorphized substrate with a dielectric layer, and replacing the semiconductor plug with a backside source contact. By performing the PAI process, crystalline semiconductor is amorphized and may be substantially removed. Thus, the performance and reliability of the semiconductor structure may be advantageously improved.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yu Huang, Chen-Ming Lee, I-Wen Wu, Fu-Kai Yang, Mei-Yun Wang
  • Integrated circuits having protruding interconnect conductors
    Patent number: 11728397
    Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes an inter-level dielectric layer. A first contact that includes a fill material is formed that extends through the inter-level dielectric layer. The inter-level dielectric layer is recessed such that the fill material extends above a top surface of the inter-level dielectric layer. An etch-stop layer is formed on the inter-level dielectric layer such that the fill material of the first contact extends into the etch-stop layer. A second contact is formed extending through the etch-stop layer to couple to the first contact. In some such examples, the second contact physically contacts a top surface and a side surface of the first contact.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hung Tsai, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Semiconductor device with backside spacer and methods of forming the same
    Patent number: 11721626
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Yu Huang, Chia-Hsien Yao, Fu-Kai Yang, Mei-Yun Wang
  • Backside Via With A Low-K Spacer
    Publication number: 20230238284
    Abstract: A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes two stacks of channel members; a source/drain feature extending between the two stacks of channel members along a direction; a source/drain contact disposed under and electrically coupled to the source/drain feature; two gate structures over and interleaved with the two stacks of channel members; a low-k spacer horizontally surrounding the source/drain contact; and a dielectric layer horizontally surrounding the low-k spacer.
    Type: Application
    Filed: March 27, 2023
    Publication date: July 27, 2023
    Inventors: Po-Yu Huang, I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang