Patents by Inventor Kailash Gopalakrishnan

Kailash Gopalakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9472641
    Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.
    Type: Grant
    Filed: April 11, 2015
    Date of Patent: October 18, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Tze-Chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari
  • Patent number: 9430240
    Abstract: Embodiments relate to pre-computation slice (p-slice) merging for prefetching in a computer processor. An aspect includes determining a plurality of p-slices corresponding to a delinquent instruction. Another aspect includes selecting a first p-slice and a second p-slice of the plurality of p-slices. Another aspect includes traversing the first p-slice and the second p-slice to determine that divergent instructions exist between the first p-slice and the second p-slice. Another aspect includes, based on determining that divergent instructions exist between the first p-slice and the second p-slice, determining whether the first p-slice and the second p-slice converge after the divergent instructions. Another aspect includes, based on determining that the first p-slice and the second p-slice converge after the divergent instructions, merging the first p-slice and the second p-slice into a single merged p-slice.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: August 30, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Islam Atta, Ioana M. Baldini Soares, Kailash Gopalakrishnan, Vijayalakshmi Srinivasan
  • Publication number: 20160197294
    Abstract: An apparatus with a programmable response includes a semiconductor device with a junction formed thereon, the junction having a built-in potential, a quantum well element proximate to the junction that provides an energy well within a depletion region of the junction. The energy well comprises one or more donor energy states that support electron trapping, and/or one or more acceptor energy states that support hole trapping; thereby modulating the built-in potential of the junction. The semiconductor device may be a diode, a bipolar diode, a transistor, or the like. A corresponding method is also disclosed herein.
    Type: Application
    Filed: February 16, 2016
    Publication date: July 7, 2016
    Inventors: Ali Afzali-Ardakani, Tze-chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari, Young H. Kwark
  • Publication number: 20160197296
    Abstract: An apparatus with a programmable response includes a semiconductor device with a junction formed thereon, the junction having a built-in potential, a quantum well element proximate to the junction that provides an energy well within a depletion region of the junction. The energy well comprises one or more donor energy states that support electron trapping, and/or one or more acceptor energy states that support hole trapping; thereby modulating the built-in potential of the junction. The semiconductor device may be a diode, a bipolar diode, a transistor, or the like. A corresponding method is also disclosed herein.
    Type: Application
    Filed: February 15, 2016
    Publication date: July 7, 2016
    Inventors: Ali Afzali-Ardakani, Tze-chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari, Young H. Kwark
  • Patent number: 9379340
    Abstract: An apparatus with a programmable response includes a semiconductor device with a junction formed thereon, the junction having a built-in potential, a quantum well element proximate to the junction that provides an energy well within a depletion region of the junction. The energy well comprises one or more donor energy states that support electron trapping, and/or one or more acceptor energy states that support hole trapping; thereby modulating the built-in potential of the junction. The semiconductor device may be a diode, a bipolar diode, a transistor, or the like. A corresponding method is also disclosed herein.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: June 28, 2016
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Tze-chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari, Young H. Kwark
  • Patent number: 9379342
    Abstract: An apparatus with a programmable response includes a semiconductor device with a junction formed thereon, the junction having a built-in potential, a quantum well element proximate to the junction that provides an energy well within a depletion region of the junction. The energy well comprises one or more donor energy states that support electron trapping, and/or one or more acceptor energy states that support hole trapping; thereby modulating the built-in potential of the junction. The semiconductor device may be a diode, a bipolar diode, a transistor, or the like. A corresponding method is also disclosed herein.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: June 28, 2016
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Tze-chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari, Young H. Kwark
  • Patent number: 9318572
    Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.
    Type: Grant
    Filed: September 5, 2015
    Date of Patent: April 19, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Tze-Chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari
  • Patent number: 9318717
    Abstract: An apparatus with a programmable response includes a semi-conductor device with a junction formed thereon, the junction having a built-in potential, a quantum well element proximate to the junction that provides an energy well within a depletion region of the junction. The energy well comprises one or more donor energy states that support electron trapping, and/or one or more acceptor energy states that support hole trapping; thereby modulating the built-in potential of the junction. The semi-conductor device may be a diode, a bipolar diode, a transistor, or the like. A corresponding method is also disclosed herein.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: April 19, 2016
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Tze-chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari, Young H. Kwark
  • Patent number: 9305650
    Abstract: A dense binary memory switch device combines the function of a pass transistor and a memory cell and has low programming and operation voltages. The device includes a charge storage region coupled to a gate electrode through a gate dielectric layer and to a channel region through a tunneling dielectric layer. The charge storage region includes a floating gate charged by tunneled carriers from the channel region. Charge retention is facilitated by the band offset between the charge storage region and the tunneling dielectric layer.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: April 5, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kailash Gopalakrishnan, Bahman Hekmatshoartabari
  • Patent number: 9246113
    Abstract: A dense binary memory switch device combines the function of a pass transistor and a memory cell and has low programming and operation voltages. The device includes a charge storage region coupled to a gate electrode through a gate dielectric layer and directly contacting a channel region. The charge storage region contains quantum structures, deep traps or combinations thereof and is charged by carriers injected from injection regions that are in direct contact with the charge storage region. Fabrication of the device at low temperatures compatible with back-end-of-line processing is further disclosed.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: January 26, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Tze-Chiang Chen, Kailash Gopalakrishnan, Wilfried Ernst-August Haensch, Bahman Hekmatshoartabari
  • Patent number: 9245896
    Abstract: A dense binary memory switch device combines the function of a pass transistor and a memory cell and has low programming and operation voltages. The device includes a charge storage region coupled to a gate electrode through a gate dielectric layer and to a channel region through another dielectric layer. The charge storage region is charged by carriers injected from injection regions that are in direct contact with the charge storage region. Fabrication of the device at low temperatures compatible with back-end-of-line processing is further disclosed.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: January 26, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Tze-Chiang Chen, Kailash Gopalakrishnan, Wilfried Ernst-August Haensch, Bahman Hekmatshoartabari
  • Publication number: 20150380517
    Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.
    Type: Application
    Filed: September 5, 2015
    Publication date: December 31, 2015
    Inventors: Ali Afzali-Ardakani, Tze-Chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari
  • Patent number: 9147615
    Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: September 29, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Tze-Chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari
  • Publication number: 20150236285
    Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.
    Type: Application
    Filed: April 11, 2015
    Publication date: August 20, 2015
    Inventors: Ali Afzali-Ardakani, Tze-Chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari
  • Publication number: 20150236027
    Abstract: A dense binary memory switch device combines the function of a pass transistor and a memory cell and has low programming and operation voltages. The device includes a charge storage region coupled to a gate electrode through a gate dielectric layer and to a channel region through a tunneling dielectric layer. The charge storage region includes a floating gate charged by tunneled carriers from the channel region. Charge retention is facilitated by the band offset between the charge storage region and the tunneling dielectric layer.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 20, 2015
    Applicant: International Business Machines Corporation
    Inventors: Kailash Gopalakrishnan, Bahman Hekmatshoartabari
  • Publication number: 20150236029
    Abstract: A dense binary memory switch device combines the function of a pass transistor and a memory cell and has low programming and operation voltages. The device includes a charge storage region coupled to a gate electrode through a gate dielectric layer and to a channel region through another dielectric layer. The charge storage region is charged by carriers injected from injection regions that are in direct contact with the charge storage region. Fabrication of the device at low temperatures compatible with back-end-of-line processing is further disclosed.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 20, 2015
    Applicant: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Tze-Chiang Chen, Kailash Gopalakrishnan, Wilfried Ernst-August Haensch, Bahman Hekmatshoartabari
  • Publication number: 20150236283
    Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 20, 2015
    Applicant: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Tze-Chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari
  • Publication number: 20150235123
    Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.
    Type: Application
    Filed: April 11, 2015
    Publication date: August 20, 2015
    Inventors: Ali Afzali-Ardakani, Tze-Chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari
  • Publication number: 20150236284
    Abstract: A dense binary memory switch device combines the function of a pass transistor and a memory cell and has low programming and operation voltages. The device includes a charge storage region coupled to a gate electrode through a gate dielectric layer and directly contacting a channel region. The charge storage region contains quantum structures, deep traps or combinations thereof and is charged by carriers injected from injection regions that are in direct contact with the charge storage region. Fabrication of the device at low temperatures compatible with back-end-of-line processing is further disclosed.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 20, 2015
    Applicant: International Business Machines Corporation
    Inventors: Kevin K. Chan, Tze-Chiang Chen, Kailash Gopalakrishnan, Wilfried Ernst-August Haensch, Bahman Hekmatshoartabari
  • Patent number: 8902690
    Abstract: A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kailash Gopalakrishnan, Chung H. Lam, Jing Li, Robert K. Montoye