Patents by Inventor Kam Leung
Kam Leung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20170018466Abstract: Embodiments of the invention include a method for <something> and the resulting structure. A semiconductor device including a substrate, a silicon-germanium fin formed on the substrate, a dummy gate formed on the fin, and a first set of spacers formed on the exposed sidewalls of the dummy gate is provided. Xenon is implanted into the exposed portions of the fin. A second set of spacers are formed on the exposed sidewalls of the first set of spacer. A dopant is implanted into the exposed portions of the fin. The semiconductor device is thermally annealed, such that the dopants diffuse into the adjacent portions of the fin. The dummy gate is replaced with a gate structure.Type: ApplicationFiled: September 29, 2016Publication date: January 19, 2017Inventors: Kangguo Cheng, Pouya Hashemi, Kam-Leung Lee, Alexander Reznicek
-
Patent number: 9514997Abstract: Embodiments of the invention include a method for forming a FinFET device and the resulting structure. A semiconductor device including a substrate, a silicon-germanium fin formed on the substrate, a dummy gate formed on the fin, and a first set of spacers formed on the exposed sidewalls of the dummy gate is provided. Xenon is implanted into the exposed portions of the fin. A second set of spacers are formed on the exposed sidewalls of the first set of spacer. A dopant is implanted into the exposed portions of the fin. The semiconductor device is thermally annealed, such that the dopants diffuse into the adjacent portions of the fin. The dummy gate is replaced with a gate structure.Type: GrantFiled: March 25, 2015Date of Patent: December 6, 2016Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Pouya Hashemi, Kam-Leung Lee, Alexander Reznicek
-
Publication number: 20160284606Abstract: Embodiments of the invention include a method for <something> and the resulting structure. A semiconductor device including a substrate, a silicon-germanium fin formed on the substrate, a dummy gate formed on the fin, and a first set of spacers formed on the exposed sidewalls of the dummy gate is provided. Xenon is implanted into the exposed portions of the fin. A second set of spacers are formed on the exposed sidewalls of the first set of spacer. A dopant is implanted into the exposed portions of the fin. The semiconductor device is thermally annealed, such that the dopants diffuse into the adjacent portions of the fin. The dummy gate is replaced with a gate structure.Type: ApplicationFiled: March 25, 2015Publication date: September 29, 2016Inventors: Kangguo Cheng, Pouya Hashemi, Kam-Leung Lee, Alexander Reznicek
-
Patent number: 9406569Abstract: A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough.Type: GrantFiled: October 21, 2014Date of Patent: August 2, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Gregory G. Freeman, Kam Leung Lee, Chengwen Pei, Geng Wang, Yanli Zhang
-
Patent number: 9240354Abstract: A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough.Type: GrantFiled: November 14, 2012Date of Patent: January 19, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Gregory G. Freeman, Kam Leung Lee, Chengwen Pei, Geng Wang, Yanli Zhang
-
Patent number: 9196712Abstract: A semiconductor device fabrication process includes forming a fin upon a semiconductor substrate and forming a gate upon the semiconductor substrate and upon and orthogonal to the fin, forming a source drain contacts by growing epitaxy material over the fin, forming a trench between the epitaxy material and a gate to expose an upper surface portion of the fin, doping the exposed fin portion to form an extension region, and activating the extension region. The semiconductor device may include the fin, gate, gate spacers upon sidewalls of the gate, a source drain contact adjacent to the gate spacers surrounding the fin, and doped extension regions within the fin below the gate spacers.Type: GrantFiled: September 12, 2014Date of Patent: November 24, 2015Assignee: GlobalFoundries Inc.Inventors: Mohammad Hasanuzzaman, Jeffrey B. Johnson, Kam-Leung Lee
-
Patent number: 9105559Abstract: A conformal doping process for FinFET devices on a semiconductor substrate which includes NFET fins and PFET fins. In a first exemplary embodiment, an N-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in an N-type dopant from the N-type dopant composition into the NFET fins. A P-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in a P-type dopant from the P-type dopant composition into the PFET fins. In a second exemplary embodiment, one of the NFET fins and PFET fins may be covered with a first dopant composition and then a second dopant composition may cover both the NFET fins and the PFET fins followed by an anneal to drive in both dopants.Type: GrantFiled: September 16, 2013Date of Patent: August 11, 2015Assignees: International Business Machines Corporation, Global Foundries, Inc.Inventors: Veeraraghavan S. Basker, Nathaniel Berliner, Hyun-Jin Cho, Johnathan Faltermeier, Kam-Leung Lee, Tenko Yamashita
-
Patent number: 9064336Abstract: A machine readable storage media containing executable program instructions which when executed cause a digital processing system to set a plurality of operands and operators. A plurality of texture maps are sent to a processor for texture compositing. Operands are selected for a texture operation. A first logic is used wherein if the circulation of blend stages is equal to a number of blend stages, then a color saturation is performed, and a second logic that if the circulation number of blend stages does not equal the number of blend stages then at least one operand is selected for another texture compositing operation.Type: GrantFiled: August 24, 2007Date of Patent: June 23, 2015Assignee: Intel CorporationInventors: Kam Leung, Val G. Cook, Peter L. Doyle, Wing Hang Wong
-
Publication number: 20150079773Abstract: A conformal doping process for FinFET devices on a semiconductor substrate which includes NFET fins and PFET fins. In a first exemplary embodiment, an N-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in an N-type dopant from the N-type dopant composition into the NFET fins. A P-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in a P-type dopant from the P-type dopant composition into the PFET fins. In a second exemplary embodiment, one of the NFETfins and PFET fins may be covered with a first dopant composition and then a second dopant composition may cover both the NFET fins and the PFET fins followed by an anneal to drive in both dopants.Type: ApplicationFiled: September 16, 2013Publication date: March 19, 2015Applicants: GLOBALFOUNDRIES Inc., International Business Machines CorporationInventors: Veeraraghavan S. Basker, Nathaniel Berliner, Hyun-Jin Cho, Johnathan Faltermeler, Kam-Leung Lee, Tenko Yamashita
-
Publication number: 20150056760Abstract: A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough.Type: ApplicationFiled: October 21, 2014Publication date: February 26, 2015Inventors: Gregory G. Freeman, Kam Leung Lee, Chengwen Pei, Geng Wang, Yanli Zhang
-
Patent number: 8927422Abstract: A method for forming a raised silicide contact including depositing a layer of silicon at a bottom of a contract trench using a gas cluster implant technique which accelerates clusters of silicon atoms causing them to penetrate a surface oxide on a top surface of the silicide, a width of the silicide and the contact trench are substantially equal; heating the silicide including the silicon layer to a temperature from about 300° C. to about 950° C. in an inert atmosphere causing silicon from the layer of silicon to react with the remaining silicide partially formed in the silicon containing substrate; and forming a raised silicide from the layer of silicon, wherein the thickness of the raised silicide is greater than the thickness of the silicide and the raised silicide protrudes above a top surface of the silicon containing substrate.Type: GrantFiled: June 18, 2012Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Emre Alptekin, Nathaniel Berliner, Christian Lavoie, Kam-Leung Lee, Ahmet Serkan Ozcan
-
Publication number: 20140131782Abstract: A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough.Type: ApplicationFiled: November 14, 2012Publication date: May 15, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory G. Freeman, Kam Leung Lee, Chengwen Pei, Geng Wang, Yanli Zhang
-
Publication number: 20130334693Abstract: A method for forming a raised silicide contact, the method including depositing a layer of silicon using a gas cluster implant technique which accelerates clusters of silicon atoms causing them to penetrate a surface oxide on a top surface of the silicide; heating the silicide including the silicon layer to a temperature from about 300° C. to about 950° and holding the temperature for about 0.1 miliseconds to about 600 seconds in an inert atmosphere causing silicon from the layer of silicon to react with the remaining silicide partially formed in the silicon containing substrate; and forming a raised silicide from the layer of silicon, wherein the thickness of the raised silicide is greater than the thickness of the silicide and the raised silicide protrudes above a top surface of the silicon containing substrate.Type: ApplicationFiled: June 18, 2012Publication date: December 19, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Emre Alptekin, Nathaniel Berliner, Christian Lavoie, Kam-Leung Lee, Ahmet Serkan Ozcan
-
Publication number: 20120190216Abstract: A semiconductor structure is provided. In some cases, an absorber having a low deposition temperature is applied to at least a portion of the structure. At least a portion of the structure is subjected to a long flash anneal process.Type: ApplicationFiled: April 29, 2011Publication date: July 26, 2012Applicant: International Business Machines CorporationInventors: Kevin K. Chan, Eric C. Harley, Isaac Lauer, Kam-Leung Lee, Paul A. Ronsheim
-
Patent number: 8230270Abstract: The invention relates to a monitoring device for a processor comprising a means for monitoring the power consumption of the processor and a means for analysing the power consumption to detect abnormal operation of the processor.Type: GrantFiled: May 9, 2008Date of Patent: July 24, 2012Assignee: University of LeicesterInventors: Michael Joseph Pont, Kam Leung Chan
-
Patent number: 8114748Abstract: A method of forming a semiconductor device is provided that includes forming a gate structure atop a substrate and implanting dopants into the substrate to a depth of 10 nm or less from an upper surface of the substrate. In a following step, an anneal is performed with a peak temperature ranging from 1200° C. to 1400° C., and a hold time period ranging from 1 millisecond to 5 milliseconds.Type: GrantFiled: June 25, 2009Date of Patent: February 14, 2012Assignee: International Business Machines CorporationInventors: Kam-Leung Lee, Paul A. Ronsheim
-
Publication number: 20110254138Abstract: An improved low-temperature absorber, amorphous carbonitride (ACN) with an extinction coefficient (k) of greater than 0.15, and an emissivity of greater than 0.8 is disclosed. The ACN film can also be characterized as having a minimum of hydrocarbon content as observed by FTIR. The ACN film can be used as an effective absorbing layer that absorbs a wide range of electromagnetic radiation from different sources including lasers or flash lamps. A method of forming such an ACN film at a deposition temperature of less than, or equal to, 450° C. is also provided.Type: ApplicationFiled: April 15, 2010Publication date: October 20, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Katherina E. Babich, Pratik P. Joshi, Kam Leung Lee, Deborah A. Neumayer, Spyridon Skordas
-
Publication number: 20100327375Abstract: A method of forming a semiconductor device is provided that includes forming a gate structure atop a substrate and implanting dopants into the substrate to a depth of 10 nm or less from an upper surface of the substrate. In a following step, an anneal is performed with a peak temperature ranging from 1200° C. to 1400° C., and a hold time period ranging from 1 millisecond to 5 milliseconds.Type: ApplicationFiled: June 25, 2009Publication date: December 30, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kam-Leung Lee, Paul A. Ronsheim
-
Publication number: 20100281298Abstract: The invention relates to a monitoring device for a processor comprising a means for monitoring the power consumption of the processor and a means for analysing the power consumption to detect abnormal operation of the processor.Type: ApplicationFiled: May 9, 2008Publication date: November 4, 2010Inventors: Michael Joseph Pont, Kam Leung Chan
-
Patent number: 7705345Abstract: A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.Type: GrantFiled: January 7, 2004Date of Patent: April 27, 2010Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Kevin K. Chan, Dureseti Chidambarrao, Silke H. Christianson, Jack O. Chu, Anthony G. Domenicucci, Kam-Leung Lee, Anda C. Mocuta, John A. Ott, Qiqing C. Ouyang