Patents by Inventor Kameran Azadet

Kameran Azadet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for multi-band digital pre-distortion using a canonical form with reduced dimension look-up table
    Patent number: 12348251
    Abstract: A system and method for multi-band digital pre-distortion (DPD) for a non-linear system. The system includes a DPD circuitry configured to perform multi-band DPD on a multi-band input signal to compensate for a non-linearity of a non-linear system. The multi-band input signal includes input signals of multiple frequency bands and the DPD circuitry is configured to perform DPD on an input signal of each frequency band per frequency band. The DPD circuitry is configured to perform the DPD using a combination of a look-up table (LUT) that evaluates a non-linear function and computation of terms of a non-linear polynomial of one or more variables representing the input signals of multiple frequency bands. Both the non-linear function and the non-linear polynomial are in a reduced dimension lower than a dimension of the multi-band input signal.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: July 1, 2025
    Assignee: Intel Corporation
    Inventor: Kameran Azadet
  • Method and apparatus for digital pre-distortion adaptation
    Publication number: 20250211265
    Abstract: A method and apparatus configured for digital pre-distortion (DPD) adaptation. The apparatus may include DPD circuitry and DPD adaptation circuitry. The DPD circuitry is configured to process input data using a pre-distortion function to generate pre-processed input data that is to be subsequently processed by a non-linear system. The pre-distortion function is represented as a sum of a plurality of non-linear terms, and non-linear effects of the non-linear system are compensated by the DPD circuitry. The DPD adaptation circuitry is configured to adapt coefficients of the DPD circuitry based on feedback information derived from an output signal of the non-linear system. The DPD adaptation circuitry is configured to adapt the plurality of non-linear terms of the pre-distortion function one non-linear term at a time. The pre-distortion function may be evaluated using look-up tables (LUTs). The LUTs may be adapted one LUT at a time in a round robin fashion.
    Type: Application
    Filed: December 20, 2023
    Publication date: June 26, 2025
    Inventors: Kameran AZADET, Ramon SANCHEZ, Hazar YUKSEL, Kannan RAJAMANI, Zoran ZIVKOVIC, Albert MOLINA
  • Digital pre-distortion (DPD) adaptation using a hybrid hardware accelerator and programmable array architecture
    Patent number: 12314216
    Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, which may be implemented for the computation of pre-distortion (DPD) coefficients while maintaining flexibility for additional DPD computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, which achieves a division of functionality and connects the programmable processing array components to the hardware accelerator components without sacrificing flexibility. This results in a balance between power/area and flexibility.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: May 27, 2025
    Assignee: Intel Corporation
    Inventors: Zoran Zivkovic, Kameran Azadet, Kannan Rajamani, Thomas Smith
  • Hybrid hardware accelerator and programmable array architecture
    Patent number: 12314217
    Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, while maintaining flexibility for additional computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, which achieves a division of functionality and connects the programmable processing array components to the hardware accelerator components without sacrificing flexibility. This results in a balance between power/area and flexibility.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: May 27, 2025
    Assignee: Intel Corporation
    Inventors: Zoran Zivkovic, Kameran Azadet, Kannan Rajamani, Thomas Smith
  • Processing device, transmitter, base station, mobile device, method and computer program
    Patent number: 12278649
    Abstract: A processing device is provided. The processing device comprises one or more interfaces configured to transmit information to a nonlinear device and processing circuitry configured to control the one or more interfaces and to. Further, the processing circuitry is configured to transmit an excitation signal to the nonlinear device and to receive response information from the nonlinear device. Further, the processing circuitry is configured to determine a linear response of the nonlinear device based on the response information and to determine a nonlinear response of the nonlinear device based on the determined linear response.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: April 15, 2025
    Assignee: Intel Corporation
    Inventors: Ramon Sanchez, Kameran Azadet, Martin Clara, Daniel Gruber
  • Method and system for digital correction for a dynamically varying non-linear system
    Patent number: 12273074
    Abstract: A system and method for digital correction for a dynamically varying non-linear system. The system includes a correction circuitry including at least one look-up table (LUT). The correction circuitry is configured to receive an input signal and modify the input signal to be processed by the non-linear system using at least one LUT to correct non-linearity incurred by the non-linear system. The at least one LUT is addressed by a magnitude or power of the input signal and a dynamically varying parameter associated with the input signal. The dynamically varying parameter may be one of average signal power of the input signal, a differential of the average power of the input signal, a directional beam index, or temperature.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: April 8, 2025
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Marc Jan Georges Tiebout, Ramon Sanchez, Hazar Yuksel
  • Method and apparatus for measuring and cancelling local oscillator feedthrough using an observation receiver
    Patent number: 12261637
    Abstract: A method and apparatus for cancelling local oscillator feedthrough (LOFT). A transmitter includes a first mixer configured to mix a transmit signal with a first local oscillator signal. An observation receiver receives a fraction of a power of the transmit signal as a feedback signal and processes the feedback signal. The observation receiver includes a second mixer configured to mix the feedback signal with a second local oscillator signal. A LOFT correction estimation circuitry is configured to determine a DC offset to cancel LOFT at the first mixer in the transmitter based on measurements on outputs of the second mixer. An LOFT correction circuitry is configured to add the DC offset to the transmit signal. The LOFT correction estimation circuitry may determine the DC offset based on several measurements obtained by varying the DC offset and a phase shift in the second local oscillator signal in the observation receiver.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: March 25, 2025
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Marc Jan Georges Tiebout
  • Wireless communication technology, apparatuses, and methods
    Patent number: 12237589
    Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: February 25, 2025
    Assignee: Intel Corporation
    Inventors: Erkan Alpman, Arnaud Lucres Amadjikpe, Omer Asaf, Kameran Azadet, Rotem Banin, Miroslav Baryakh, Anat Bazov, Stefano Brenna, Bryan K. Casper, Anandaroop Chakrabarti, Gregory Chance, Debabani Choudhury, Emanuel Cohen, Claudio Da Silva, Sidharth Dalmia, Saeid Daneshgar Asl, Kaushik Dasgupta, Kunal Datta, Brandon Davis, Ofir Degani, Amr M. Fahim, Amit Freiman, Michael Genossar, Eran Gerson, Eyal Goldberger, Eshel Gordon, Meir Gordon, Josef Hagn, Shinwon Kang, Te Yu Kao, Noam Kogan, Mikko S. Komulainen, Igal Yehuda Kushnir, Saku Lahti, Mikko M. Lampinen, Naftali Landsberg, Wook Bong Lee, Run Levinger, Albert Molina, Resti Montoya Moreno, Tawfiq Musah, Nathan G. Narevsky, Hosein Nikopour, Oner Orhan, Georgios Palaskas, Stefano Pellerano, Ron Pongratz, Ashoke Ravi, Shmuel Ravid, Peter Andrew Sagazio, Eren Sasoglu, Lior Shakedd, Gadi Shor, Baljit Singh, Menashe Soffer, Ra'anan Sover, Shilpa Talwar, Nebil Tanzi, Moshe Teplitsky, Chintan S. Thakkar, Jayprakash Thakur, Avi Tsarfati, Yossi Tsfati, Marian Verhelst, Nir Weisman, Shuhei Yamada, Ana M. Yepes, Duncan Kitchin
  • Method and system for digital equalization of a linear or non-linear system
    Patent number: 12206426
    Abstract: A system and method for equalization of a linear or non-linear system. The system includes an adder configured to add an analog reference signal and an input signal, a processing system configured to process a sum of the analog reference signal and the input signal, a non-linear equalizer (NLEQ) configured to process an output of the processing system to remove a distortion incurred by the processing system, a calibration circuitry configured to generate a reconstructed reference signal in digital domain based on measurement of the analog reference signal, and generate coefficients for the NLEQ based on the reconstructed reference signal and the output of the processing system, and a subtractor configured to subtract the reconstructed reference signal from an output of the NLEQ. The analog reference signal may be a sinusoid including single or multiple tones of sinusoids. The non-linear system may be an analog-to-digital converter (ADC).
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: January 21, 2025
    Assignee: Intel Corporation
    Inventors: Albert Molina, Martin Clara, Kameran Azadet
  • Chip-to-chip interface of a multi-chip module (MCM)
    Patent number: 12182047
    Abstract: A chip-to-chip interface of a multi-chip module (MCM), including: bidirectional data links for transmitting data signals and a direction indicator bit, wherein the direction indicator bit switches a direction of the bidirectional data links in real-time; a clock link for transmitting a clock signal common to the bidirectional data links, wherein the data and clock links are comprised of conductive traces between the chips and laid out to be of substantially equal length; and a clock driver means having a digitally programmable clock signal delay.
    Type: Grant
    Filed: December 26, 2020
    Date of Patent: December 31, 2024
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Wee Liew, Ramani Tatikola, Edwin Thaller, Patrick Torta, Yu-Shan Wang, Georg Weber, James Yoder
  • Semiconductor devices, transceiver, base station and mobile device
    Patent number: 12170526
    Abstract: A semiconductor device comprising at least one transmit path is provided. The transmit path comprises an input node for receiving a digital baseband signal. Further, the transmit path comprises digital mixer circuitry coupled to the input node and configured to generate an upconverted digital baseband signal by upconverting a frequency of the digital baseband signal. Additionally, the transmit path comprises Digital-to-Analog Converter (DAC) circuitry coupled to the digital mixer circuitry and configured to generate an analog radio frequency signal based on the upconverted digital baseband signal. The transmit path comprises first analog mixer circuitry coupleable to an output of the DAC circuitry, and second analog mixer circuitry coupleable to the output of the DAC circuitry. Further, the transmit path comprises a first output node coupleable to an output of the first analog mixer circuitry, and a second output node coupleable to an output of the second analog mixer circuitry.
    Type: Grant
    Filed: November 11, 2022
    Date of Patent: December 17, 2024
    Assignee: Intel Corporation
    Inventors: Daniel Gruber, Kameran Azadet, Martin Clara, Marc Jan Georges Tiebout
  • PROCESSING PIPELINE WITH ZERO LOOP OVERHEAD
    Publication number: 20240345839
    Abstract: Techniques are disclosed for reducing or eliminating loop overhead caused by function calls in processors that form part of a pipeline architecture. The processors in the pipeline process data blocks in an iterative fashion, with each processor in the pipeline completing one of several iterations associated with a processing loop for a commonly-executed function. The described techniques leverage the use of message passing for pipelined processors to enable an upstream processor to signal to a downstream processor when processing has been completed, and thus a data block is ready for further processing in accordance with the next loop processing iteration. The described techniques facilitate a zero loop overhead architecture, enable continuous data block processing, and allow the processing pipeline to function indefinitely within the main body of the processing loop associated with the commonly-executed function where efficiency is greatest.
    Type: Application
    Filed: April 26, 2024
    Publication date: October 17, 2024
    Inventors: Kameran Azadet, Jeroen Leijten, Joseph Williams
  • Vector processor supporting linear interpolation on multiple dimensions
    Patent number: 12106101
    Abstract: Techniques are disclosed for a vector processor architecture that enables data interpolation in accordance with multiple dimensions, such as one-, two-, and three-dimensional linear interpolation. The vector processor architecture includes a vector processor and accompanying vector addressable memory that enable a simultaneous retrieval of multiple entries in the vector addressable memory to facilitate linear interpolation calculations. The vector processor architecture vastly increases the speed in which such calculations may occur compared to conventional processing architectures. Example implementations include the calculation of digital pre-distortion (DPD) coefficients for use with radio frequency (RF) transmitter chains to support multi-band applications.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: October 1, 2024
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Joseph Williams, Zoran Zivkovic
  • APPARATUS AND METHOD FOR EQUALIZING A DIGITAL INPUT SIGNAL, RECEIVER, BASE STATION AND MOBILE DEVICE
    Publication number: 20240283678
    Abstract: An apparatus for equalizing a digital input signal is provided. The apparatus includes an input node configured to receive the digital input signal. Further, the apparatus includes a plurality of filters coupled in parallel to the input node. The plurality of filters are configured to filter the digital input signal and generate a respective filtered signal. Additionally, the apparatus includes a combiner circuit coupled to the plurality of filters. The combiner circuit is configured to receive the respective filtered signal from the plurality of filters, and to generate an equalized signal by combining the received filtered signals according to a non-linear equalization function.
    Type: Application
    Filed: December 22, 2021
    Publication date: August 22, 2024
    Inventors: Albert MOLINA, Kameran AZADET, Martin CLARA
  • Method and apparatus for in-phase and quadrature imbalance correction in a frequency domain
    Patent number: 12068904
    Abstract: An apparatus and method for in-phase/quadrature (I/Q) imbalance correction in a transceiver. The apparatus includes an I/Q imbalance correction circuit and a correction coefficient generation circuit. The I/Q imbalance correction circuit is configured to modify I/Q data in a frequency domain using correction coefficients to generate corrected I/Q data. The correction coefficient generation circuit is configured to generate the correction coefficients for the I/Q imbalance correction circuit based on the I/Q data and reference data.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: August 20, 2024
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Marc Jan Georges Tiebout
  • Analog-to-digital converter and method for calibrating the same, method for calibrating a pipelined analog-to-digital converter, receiver, base station and mobile device
    Patent number: 12063050
    Abstract: An analog-to-digital converter comprising a plurality of sampling cells. At least one of the plurality of sampling cells comprises a capacitive element coupled to a cell output of the at least one of the plurality of sampling cells, wherein a cell output signal is provided at the cell output. The at least one of the plurality of sampling cells further comprises a first cell input for receiving an input signal to be digitized, and a second cell input for receiving a calibration signal. Additionally, the at least one of the plurality of sampling cells comprises a first switch circuit capable of selectively coupling the first cell input to the capacitive element based on a clock signal, and a second switch circuit capable of selectively coupling the second cell input to the capacitive element, wherein a size of the second switch circuit is smaller than a size of the first switch circuit.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 13, 2024
    Assignee: Intel Corporation
    Inventors: Albert Molina, Kameran Azadet, Martin Clara, Matteo Camponeschi, Christian Lindholm
  • Wireless communication system and base station
    Patent number: 12057871
    Abstract: A wireless communication system including a phased array comprising a plurality of antennas configured to emit a respective radio wave based on a respective antenna signal. Further, the system includes a plurality of power amplifiers each coupled to one of the plurality of antennas via a feed line and configured to output the antenna signal to the feed line. Also, the system includes a plurality of directional couplers each coupled into one of the feed lines and comprising a third port configured to output a fraction of a power received at a first port coupled to the power amplifier via the feed line, likewise a fourth port configured to output a fraction of a power received at a second port. Additionally, the system includes switching circuitry configured to alternately couple the third port to a first feedback receiver, and to alternately couple the fourth port to a second feedback receiver.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: August 6, 2024
    Assignee: Intel Corporation
    Inventors: Marc Jan Georges Tiebout, Hazar Yuksel, Kameran Azadet
  • WIRELESS COMMUNICATION TECHNOLOGY, APPARATUSES, AND METHODS
    Publication number: 20240243477
    Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.
    Type: Application
    Filed: February 15, 2024
    Publication date: July 18, 2024
    Inventors: Erkan Alpman, Arnaud Lucres Amadjikpe, Omer Asaf, Kameran Azadet, Rotem Banin, Miroslav Baryakh, Anat Bazov, Stefano Brenna, Bryan K. Casper, Anandaroop Chakrabarti, Gregory Chance, Debabani Choudhury, Emanuel Cohen, Claudio Da Silva, Sidharth Dalmia, Saeid Daneshgar Asl, Kaushik Dasgupta, Kunal Datta, Ofir Degani, Amr M. Fahim, Amit Freiman, Michael Genossar, Eran Gerson, Eyal Goldberger, Eshel Gordon, Meir Gordon, Josef Hagn, Shinwon Kang, Te Yu Kao, Noam Kogan, Mikko S. Komulainen, Igal Yehuda Kushnir, Saku Lahti, Mikko M. Lampinen, Naftali Landsberg, Wook Bong Lee, Run Levinger, Albert Molina, Resti Montoya Moreno, Tawfiq Musah, Nathan G. Narevsky, Hosein Nikopour, Oner Orhan, Georgios Palaskas, Stefano Pellerano, Ron Pongratz, Ashoke Ravi, Shmuel Ravid, Peter Andrew Sagazio, Eren Sasoglu, Lior Shakedd, Gadi Shor, Baljit Singh, Menashe Soffer, Ra'anan Sover, Shilpa Talwar, Nebil Tanzi, Moshe Teplitsky, Chintan S. Thakkar, Jayprakash Thakur, Avi Tsarfati, Marian Verhelst, Yossi Tsfati, Nir Weisman, Shuhei Yamada, Ana M. Yepes, Duncan Kitchin
  • Apparatus for correcting a mismatch, digital-to-analog converter system, transmitter, base station, mobile device and method for correcting a mismatch
    Patent number: 12034450
    Abstract: An apparatus for correcting a mismatch between a first segment and a second segment of a Digital-to-Analog Converter, DAC, is provided. The first segment generates a first contribution to an analog output signal of the DAC based on a first number of bits of a digital input word for the DAC converter, and the second segment generates a second contribution based on a second number of bits. Further, the apparatus comprises a first processing circuit for the first number of bits comprising a first filter configured to modify the first number of bits to generate first modified bits, and a second processing circuit comprising a second filter to modify the second number of bits to generate second modified bits. The apparatus additionally comprises an output configured to output a modified digital input word for the DAC, which is based on the first modified bits and the second modified bits.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: July 9, 2024
    Assignee: Intel Corporation
    Inventors: Daniel Gruber, Ramon Sanchez, Kameran Azadet, Martin Clara
  • APPARATUSES AND METHODS FOR DETERMINING WHETHER A PREDISTORTION IS TO BE UPDATED
    Publication number: 20240223229
    Abstract: An apparatus is proposed comprising interface circuitry configured to receive a plurality of samples causing an output signal of a power amplifier. The apparatus further comprises processing circuitry configured to allocate at least one sample of the plurality of samples to a bin based on a characteristic of the at least one sample and determine whether a predistortion for samples allocated to the bin is to be updated based on a number of samples allocated to the bin.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: Albert MOLINA, Kameran AZADET, Hazar YUKSEL